Lines Matching refs:if_id
87 u32 if_id, u32 cl_value, u32 cwl_value);
89 static int is_bus_access_done(u32 dev_num, u32 if_id,
96 u32 if_id, enum hws_ddr_freq frequency);
98 u32 if_id, enum hws_ddr_freq frequency);
182 u32 if_id, enum hws_access_type phy_access,
185 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
186 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
207 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
214 data = (tm->interface_params[if_id].bus_width == in ddr3_tip_configure_cs()
217 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
220 mem_index = tm->interface_params[if_id].memory_size; in ddr3_tip_configure_cs()
224 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
231 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
237 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
246 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
252 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
263 static int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num) in calc_cs_num() argument
275 cs_bitmask = tm->interface_params[if_id]. in calc_cs_num()
287 if_id, bus_cnt, cs_count, in calc_cs_num()
302 u32 if_id; in hws_ddr3_tip_init_controller() local
329 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
330 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_init_controller()
332 ("active IF %d\n", if_id)); in hws_ddr3_tip_init_controller()
339 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
346 if_id, CS_ENABLE_REG, 0, in hws_ddr3_tip_init_controller()
351 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
354 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
358 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
387 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
393 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
403 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
408 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
416 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
420 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
426 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
444 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
459 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
464 (tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
473 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
478 if_id, cs_mask)); in hws_ddr3_tip_init_controller()
486 ddr3_tip_configure_cs(dev_num, if_id, cs_cnt, in hws_ddr3_tip_init_controller()
502 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
505 tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
515 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
519 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
540 ((tm->interface_params[if_id]. in hws_ddr3_tip_init_controller()
544 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
550 ddr3_tip_write_odt(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
552 ddr3_tip_set_timing(dev_num, access_type, if_id, freq); in hws_ddr3_tip_init_controller()
555 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
562 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
569 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
573 timing = tm->interface_params[if_id].timing; in hws_ddr3_tip_init_controller()
583 (dev_num, if_id, &cs_num)); in hws_ddr3_tip_init_controller()
588 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
599 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
603 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
606 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
612 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
616 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
619 (data_read[if_id] == 0) ? (1 << 11) : 0; in hws_ddr3_tip_init_controller()
621 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
640 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
641 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_init_controller()
642 CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id)); in hws_ddr3_tip_init_controller()
645 CHECK_STATUS(ddr3_tip_pad_inv(dev_num, if_id)); in hws_ddr3_tip_init_controller()
650 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
653 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
675 u32 if_id; in hws_ddr3_tip_load_topology_map() local
691 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_load_topology_map()
692 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in hws_ddr3_tip_load_topology_map()
694 tm->interface_params[if_id].speed_bin_index; in hws_ddr3_tip_load_topology_map()
701 tm->interface_params[if_id]. in hws_ddr3_tip_load_topology_map()
703 tm->interface_params[if_id]. in hws_ddr3_tip_load_topology_map()
706 if (tm->interface_params[if_id].cas_l == 0) { in hws_ddr3_tip_load_topology_map()
707 tm->interface_params[if_id].cas_l = in hws_ddr3_tip_load_topology_map()
711 if (tm->interface_params[if_id].cas_wl == 0) { in hws_ddr3_tip_load_topology_map()
712 tm->interface_params[if_id].cas_wl = in hws_ddr3_tip_load_topology_map()
723 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rank_control() argument
730 if ((tm->interface_params[if_id]. in ddr3_tip_rank_control()
732 tm->interface_params[if_id]. in ddr3_tip_rank_control()
734 (tm->interface_params[if_id]. in ddr3_tip_rank_control()
736 tm->interface_params[if_id]. in ddr3_tip_rank_control()
743 data_value |= tm->interface_params[if_id]. in ddr3_tip_rank_control()
745 data_value |= tm->interface_params[if_id]. in ddr3_tip_rank_control()
749 (dev_num, ACCESS_TYPE_UNICAST, if_id, RANK_CTRL_REG, in ddr3_tip_rank_control()
758 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id) in ddr3_tip_pad_inv() argument
765 if (tm->interface_params[if_id]. in ddr3_tip_pad_inv()
769 if_id, bus_cnt, in ddr3_tip_pad_inv()
775 if (tm->interface_params[if_id]. in ddr3_tip_pad_inv()
786 if_id, ck_swap_pup_ctrl, in ddr3_tip_pad_inv()
901 u32 if_id, u32 reg_addr, u32 data_value, u32 mask) in ddr3_tip_if_write() argument
906 if_id, reg_addr, in ddr3_tip_if_write()
917 u32 if_id, u32 reg_addr, u32 *data, u32 mask) in ddr3_tip_if_read() argument
922 if_id, reg_addr, in ddr3_tip_if_read()
933 u32 if_id, u32 exp_value, u32 mask, u32 offset, in ddr3_tip_if_polling() argument
946 start_if = if_id; in ddr3_tip_if_polling()
947 end_if = if_id; in ddr3_tip_if_polling()
984 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read() argument
998 if_id, ACCESS_TYPE_UNICAST, in ddr3_tip_bus_read()
1002 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bus_read()
1005 data[bus_index] = (data_read[if_id] & 0xffff); in ddr3_tip_bus_read()
1009 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bus_read()
1013 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bus_read()
1020 *data = (data_read[if_id] & 0xffff); in ddr3_tip_bus_read()
1030 u32 if_id, enum hws_access_type phy_access, in ddr3_tip_bus_write() argument
1035 (dev_num, interface_access, if_id, phy_access, in ddr3_tip_bus_write()
1045 u32 if_id, enum hws_access_type phy_access, in ddr3_tip_bus_access() argument
1060 (dev_num, interface_access, if_id, PHY_REG_FILE_ACCESS, in ddr3_tip_bus_access()
1063 (dev_num, interface_access, if_id, PHY_REG_FILE_ACCESS, in ddr3_tip_bus_access()
1067 start_if = if_id; in ddr3_tip_bus_access()
1068 end_if = if_id; in ddr3_tip_bus_access()
1075 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_bus_access()
1076 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_bus_access()
1078 (dev_num, if_id, PHY_REG_FILE_ACCESS, 31)); in ddr3_tip_bus_access()
1087 static int is_bus_access_done(u32 dev_num, u32 if_id, u32 dunit_reg_adrr, in is_bus_access_done() argument
1095 (dev_num, ACCESS_TYPE_UNICAST, if_id, dunit_reg_adrr, in is_bus_access_done()
1097 rd_data = data_read[if_id]; in is_bus_access_done()
1105 (dev_num, ACCESS_TYPE_UNICAST, if_id, in is_bus_access_done()
1107 rd_data = data_read[if_id]; in is_bus_access_done()
1125 u32 data_val = 0, if_id, start_if, end_if; in ddr3_tip_bus_read_modify_write() local
1136 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_bus_read_modify_write()
1137 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_bus_read_modify_write()
1139 (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id, in ddr3_tip_bus_read_modify_write()
1143 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bus_read_modify_write()
1155 u32 if_id, enum hws_ddr_freq frequency) in adll_calibration() argument
1163 (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG, in adll_calibration()
1167 (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG, in adll_calibration()
1183 (dev_num, access_type, if_id, bus_cnt, in adll_calibration()
1187 (dev_num, access_type, if_id, bus_cnt, in adll_calibration()
1194 (dev_num, access_type, if_id, DRAM_PHY_CONFIGURATION, in adll_calibration()
1198 (dev_num, access_type, if_id, DRAM_PHY_CONFIGURATION, in adll_calibration()
1202 if (ddr3_tip_if_polling(dev_num, access_type, if_id, in adll_calibration()
1211 (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG, in adll_calibration()
1215 (dev_num, access_type, if_id, SDRAM_CONFIGURATION_REG, in adll_calibration()
1222 u32 if_id, enum hws_ddr_freq frequency) in ddr3_tip_freq_set() argument
1239 access_type, if_id, frequency)); in ddr3_tip_freq_set()
1247 start_if = if_id; in ddr3_tip_freq_set()
1248 end_if = if_id; in ddr3_tip_freq_set()
1253 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
1255 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_freq_set()
1256 cs_mask[if_id] = CS_BIT_MASK; in ddr3_tip_freq_set()
1257 training_result[training_stage][if_id] = TEST_SUCCESS; in ddr3_tip_freq_set()
1258 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_freq_set()
1259 &cs_mask[if_id]); in ddr3_tip_freq_set()
1267 for (if_id = start_if; if_id <= end_if; if_id++) { in ddr3_tip_freq_set()
1268 if (IS_ACTIVE(tm->if_act_mask, if_id) == 0) in ddr3_tip_freq_set()
1271 flow_result[if_id] = TEST_SUCCESS; in ddr3_tip_freq_set()
1273 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_freq_set()
1274 if (tm->interface_params[if_id].memory_freq == in ddr3_tip_freq_set()
1277 tm->interface_params[if_id].cas_l; in ddr3_tip_freq_set()
1279 tm->interface_params[if_id].cas_wl; in ddr3_tip_freq_set()
1290 dev_num, access_type, if_id, in ddr3_tip_freq_set()
1306 tm->interface_params[if_id]. in ddr3_tip_freq_set()
1313 if_id, in ddr3_tip_freq_set()
1320 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1324 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1329 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1333 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1339 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1342 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1345 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1348 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1354 (dev_num, access_type, if_id, DFS_REG, 0x4, in ddr3_tip_freq_set()
1358 if_id, 0x8, 0x8, DFS_REG, in ddr3_tip_freq_set()
1367 tip_set_freq_divider_func(dev_num, if_id, in ddr3_tip_freq_set()
1374 t_refi = (tm->interface_params[if_id].interface_temp == in ddr3_tip_freq_set()
1383 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1388 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1391 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1396 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1402 (dev_num, access_type, if_id, 0x1874, in ddr3_tip_freq_set()
1405 (dev_num, access_type, if_id, 0x1884, in ddr3_tip_freq_set()
1408 (dev_num, access_type, if_id, 0x1894, in ddr3_tip_freq_set()
1411 (dev_num, access_type, if_id, 0x18a4, in ddr3_tip_freq_set()
1417 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1421 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1436 if_id, bus_cnt, DDR_PHY_DATA, in ddr3_tip_freq_set()
1443 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_freq_set()
1450 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1455 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1461 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff, in ddr3_tip_freq_set()
1470 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1474 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1478 ddr3_tip_set_timing(dev_num, access_type, if_id, frequency); in ddr3_tip_freq_set()
1486 (dev_num, access_type, if_id, DFS_REG, 0, in ddr3_tip_freq_set()
1489 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG, in ddr3_tip_freq_set()
1497 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1500 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, in ddr3_tip_freq_set()
1508 (dev_num, access_type, if_id, DFS_REG, 0, in ddr3_tip_freq_set()
1512 (dev_num, access_type, if_id, DUNIT_MMASK_REG, in ddr3_tip_freq_set()
1520 (dev_num, access_type, if_id, MR0_REG, in ddr3_tip_freq_set()
1532 if_id, MR2_REG, in ddr3_tip_freq_set()
1540 if_id, ODT_TIMING_LOW, in ddr3_tip_freq_set()
1544 if_id, ODT_TIMING_HI_REG, in ddr3_tip_freq_set()
1549 if_id, in ddr3_tip_freq_set()
1569 if_id, in ddr3_tip_freq_set()
1582 u32 if_id, u32 cl_value, u32 cwl_value) in ddr3_tip_write_odt() argument
1592 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1595 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1599 if_id, in ddr3_tip_write_odt()
1605 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1615 u32 if_id, enum hws_ddr_freq frequency) in ddr3_tip_set_timing() argument
1625 speed_bin_index = tm->interface_params[if_id].speed_bin_index; in ddr3_tip_set_timing()
1626 memory_size = tm->interface_params[if_id].memory_size; in ddr3_tip_set_timing()
1628 (tm->interface_params[if_id].bus_width == in ddr3_tip_set_timing()
1663 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1667 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1670 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1673 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1676 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1679 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1682 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1685 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1688 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1691 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1694 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1749 u32 if_id; in ddr3_tip_get_first_active_if() local
1752 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_get_first_active_if()
1753 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_get_first_active_if()
1754 if (interface_mask & (1 << if_id)) { in ddr3_tip_get_first_active_if()
1755 *interface_id = if_id; in ddr3_tip_get_first_active_if()
1768 u32 if_id, bus_num, cs_bitmask, data_val, cs_num; in ddr3_tip_write_cs_result() local
1771 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_cs_result()
1772 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_cs_result()
1777 tm->interface_params[if_id]. in ddr3_tip_write_cs_result()
1781 ddr3_tip_bus_read(dev_num, if_id, in ddr3_tip_write_cs_result()
1789 if_id, in ddr3_tip_write_cs_result()
1808 u32 if_id, reg; in ddr3_tip_write_mrs_cmd() local
1814 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1815 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_mrs_cmd()
1817 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_write_mrs_cmd()
1819 (cs_mask_arr[if_id] << 8) | cmd, 0xf1f)); in ddr3_tip_write_mrs_cmd()
1822 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1823 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_write_mrs_cmd()
1824 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0, in ddr3_tip_write_mrs_cmd()
1840 u32 if_id = 0; in ddr3_tip_reset_fifo_ptr() local
1844 if_id, 0x15c8, 0, 0xff000000)); in ddr3_tip_reset_fifo_ptr()
1850 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
1854 if_id, 0x15b0, in ddr3_tip_reset_fifo_ptr()
1858 if_id, 0x1400, 0, 0x40000000)); in ddr3_tip_reset_fifo_ptr()
1861 if_id, 0x1400, in ddr3_tip_reset_fifo_ptr()
1865 if_id, TRAINING_SW_2_REG, in ddr3_tip_reset_fifo_ptr()
1869 if_id, 0x15b4, 0x10000, 0x10000)); in ddr3_tip_reset_fifo_ptr()
1879 u32 if_id, phy_id, cs; in ddr3_tip_ddr3_reset_phy_regs() local
1882 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_reset_phy_regs()
1883 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_ddr3_reset_phy_regs()
1889 if_id, ACCESS_TYPE_UNICAST, in ddr3_tip_ddr3_reset_phy_regs()
1895 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1900 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1905 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1963 u32 if_id; in ddr3_tip_ddr3_training_main_flow() local
1981 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_ddr3_training_main_flow()
1982 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_ddr3_training_main_flow()
1984 (u8)dev_num, if_id, freq); in ddr3_tip_ddr3_training_main_flow()
2380 u32 if_id, stage, ret; in ddr3_tip_ddr3_auto_tune() local
2385 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2387 training_result[stage][if_id] = NO_TEST_DONE; in ddr3_tip_ddr3_auto_tune()
2408 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2411 if (training_result[stage][if_id] == TEST_FAILED) in ddr3_tip_ddr3_auto_tune()
2418 if_id)); in ddr3_tip_ddr3_auto_tune()
2434 u32 if_id = 0, mem_mask = 0, bus_index = 0; in ddr3_tip_enable_init_sequence() local
2441 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_enable_init_sequence()
2442 VALIDATE_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_enable_init_sequence()
2445 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1, in ddr3_tip_enable_init_sequence()
2450 if_id)); in ddr3_tip_enable_init_sequence()
2460 tm->interface_params[if_id]. in ddr3_tip_enable_init_sequence()
2468 if_id, CS_ENABLE_REG, 1 << 3, in ddr3_tip_enable_init_sequence()
2551 u32 hws_ddr3_get_device_width(u32 if_id) in hws_ddr3_get_device_width() argument
2555 return (tm->interface_params[if_id].bus_width == in hws_ddr3_get_device_width()
2559 u32 hws_ddr3_get_device_size(u32 if_id) in hws_ddr3_get_device_size() argument
2563 if (tm->interface_params[if_id].memory_size >= in hws_ddr3_get_device_size()
2567 tm->interface_params[if_id].memory_size)); in hws_ddr3_get_device_size()
2570 return 1 << tm->interface_params[if_id].memory_size; in hws_ddr3_get_device_size()
2574 int hws_ddr3_calc_mem_cs_size(u32 if_id, u32 cs, u32 *cs_size) in hws_ddr3_calc_mem_cs_size() argument
2578 dev_size = hws_ddr3_get_device_size(if_id); in hws_ddr3_calc_mem_cs_size()
2581 hws_ddr3_get_device_width(if_id)) * dev_size); in hws_ddr3_calc_mem_cs_size()
2606 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr) in hws_ddr3_cs_base_adr_calc() argument
2614 if (hws_ddr3_calc_mem_cs_size(if_id, cs, &cs_mem_size) != MV_OK) in hws_ddr3_cs_base_adr_calc()
2638 hws_ddr3_get_device_width(if_id)); in hws_ddr3_cs_base_adr_calc()