Home
last modified time | relevance | path

Searched refs:hclk (Results 1 – 25 of 45) sorted by relevance

12

/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dddr3_init.c1144 u32 tmp, hclk; in get_target_freq() local
1148 hclk = 84; in get_target_freq()
1161 hclk = 150; in get_target_freq()
1167 hclk = 165; in get_target_freq()
1171 hclk = 180; in get_target_freq()
1178 hclk = 200; in get_target_freq()
1183 hclk = 222; in get_target_freq()
1189 hclk = 250; in get_target_freq()
1195 hclk = 267; in get_target_freq()
1201 hclk = 300; in get_target_freq()
[all …]
H A Dddr3_dfs.c127 u32 hclk; in ddr3_dfs_high_2_low() local
129 get_target_freq(cpu_freq, &tmp, &hclk); in ddr3_dfs_high_2_low()
783 u32 hclk; in ddr3_dfs_low_2_high() local
785 get_target_freq(cpu_freq, &tmp, &hclk); in ddr3_dfs_low_2_high()
/rk3399_rockchip-uboot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_slc.c111 uint32_t hclk = get_hclk_clk_rate(); in lpc32xx_nand_init() local
126 TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) | in lpc32xx_nand_init()
127 TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) | in lpc32xx_nand_init()
128 TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) | in lpc32xx_nand_init()
130 TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) | in lpc32xx_nand_init()
131 TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) | in lpc32xx_nand_init()
132 TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP), in lpc32xx_nand_init()
/rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/
H A Dclock.c218 unsigned long hclk; in get_hclk_sys() local
237 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1); in get_hclk_sys()
239 return hclk; in get_hclk_sys()
/rk3399_rockchip-uboot/drivers/rng/
H A Drockchip_rng.c108 struct clk hclk; member
116 if (!pdata->hclk.dev) in rk_rng_do_enable_clk()
119 ret = enable ? clk_enable(&pdata->hclk) : clk_disable(&pdata->hclk); in rk_rng_do_enable_clk()
377 clk_get_by_index(dev, 0, &pdata->hclk); in rockchip_rng_ofdata_to_platdata()
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dddr3_init.c533 u32 tmp, hclk = 200; in get_target_freq() local
538 hclk = 200; in get_target_freq()
542 hclk = 333; in get_target_freq()
546 hclk = 400; in get_target_freq()
555 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */ in get_target_freq()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3588.dtsi99 clock-names = "mclk", "hclk";
110 clock-names = "mclk_tx", "hclk";
125 clock-names = "mclk", "hclk";
136 clock-names = "mclk_tx", "hclk";
150 clock-names = "mclk_rx", "hclk";
164 clock-names = "mclk_rx", "hclk";
178 clock-names = "mclk", "hclk";
192 clock-names = "mclk", "hclk";
H A Drv1126b-u-boot.dtsi38 clock-names = "aclk", "hclk", "pka";
48 clock-names = "hclk", "aclk";
H A Dat91sam9x5_macb1.dtsi50 clock-names = "hclk", "pclk";
H A Dsama5d3_emac.dtsi50 clock-names = "hclk", "pclk";
H A Dat91sam9x5_macb0.dtsi62 clock-names = "hclk", "pclk";
H A Dat91sam9261.dtsi81 clock-names = "ohci_clk", "hclk", "uhpck";
92 clock-names = "lcdc_clk", "hclk";
134 clock-names = "pclk", "hclk";
717 hclk0: hclk@16 {
723 hclk1: hclk@17 {
H A Drk3576.dtsi1735 clock-names = "hclk", "aclk", "dclk";
1890 clock-names = "aclk", "hclk", "sclk";
1924 clock-names = "aclk", "hclk", "sclk";
2399 clock-names = "mclk", "hclk";
2412 clock-names = "mclk", "hclk";
2426 clock-names = "mclk", "hclk";
2442 clock-names = "mclk", "hclk";
2512 clock-names = "aclk", "pclk", "hclk", "hclk_key", "pclk_trng";
2606 clock-names = "dp", "pclk", "spdif", "hclk";
2765 clock-names = "aclk", "pclk", "hclk", "hclk_key", "pclk_trng";
[all …]
H A Drk3568.dtsi829 clock-names = "clk", "pclk", "hclk";
880 clock-names = "hclk", "dclk";
951 clock-names = "aclk", "hclk", "sclk";
981 clock-names = "pclk", "hclk";
1355 clock-names = "pclk", "hclk", "hs_clk";
1393 clock-names = "pclk", "hclk", "hs_clk";
1435 clock-names = "iahb", "isfr", "cec", "ref", "hclk";
1471 clock-names = "dp", "pclk", "spdif", "hclk";
1900 clock-names = "mclk_tx", "mclk_rx", "hclk";
1917 clock-names = "mclk_tx", "mclk_rx", "hclk";
[all …]
H A Dzynq-7000.dtsi222 clock-names = "pclk", "hclk", "tx_clk";
233 clock-names = "pclk", "hclk", "tx_clk";
H A Dsama5d3_gmac.dtsi83 clock-names = "hclk", "pclk";
H A Drk3506.dtsi736 clock-names = "mclk", "hclk";
762 clock-names = "mclk", "hclk";
831 clock-names = "mclk", "hclk";
846 clock-names = "mclk", "hclk";
889 clock-names = "mclk", "hclk";
909 clock-names = "mclk", "hclk";
929 clock-names = "mclk", "hclk";
1255 clock-names = "aclk", "hclk", "core", "pka";
H A Drk3588s.dtsi1070 clock-names = "mclk", "hclk";
1081 clock-names = "mclk_tx", "hclk";
1096 clock-names = "mclk", "hclk";
1107 clock-names = "mclk_tx", "hclk";
1121 clock-names = "mclk_rx", "hclk";
1135 clock-names = "mclk", "hclk";
1401 clock-names = "mclk_tx", "mclk_rx", "hclk";
1426 clock-names = "mclk_tx", "mclk_rx", "hclk";
1521 clock-names = "hclk";
1536 clock-names = "mclk", "hclk";
[all …]
H A Dat91sam9263.dtsi877 clock-names = "hclk", "pclk";
886 clock-names = "pclk", "hclk";
1011 clock-names = "lcdc_clk", "hclk";
1038 clock-names = "ohci_clk", "hclk", "uhpck";
H A Dzynqmp.dtsi577 clock-names = "pclk", "hclk", "tx_clk";
591 clock-names = "pclk", "hclk", "tx_clk";
605 clock-names = "pclk", "hclk", "tx_clk";
619 clock-names = "pclk", "hclk", "tx_clk";
H A Drk3528.dtsi1085 clock-names = "aclk", "hclk", "sclk";
1118 clock-names = "aclk", "hclk", "sclk";
1171 clock-names = "hclk",
1679 clock-names = "mclk", "hclk";
1693 clock-names = "mclk", "hclk";
1709 clock-names = "mclk", "hclk";
1723 clock-names = "mclk", "hclk";
1758 clock-names = "mclk", "hclk";
1964 clock-names = "aclk", "hclk", "sclk", "pka";
H A Dsama5d2.dtsi38 clock-names = "ohci_clk", "hclk", "uhpck";
614 clock-names = "hclk", "pclk";
H A Dat91sam9260.dtsi871 clock-names = "hclk", "pclk";
880 clock-names = "pclk", "hclk";
1033 clock-names = "ohci_clk", "hclk", "uhpck";
/rk3399_rockchip-uboot/drivers/spi/
H A Drockchip_sfc.c184 struct clk hclk; member
354 ret = clk_get_by_index(bus, 1, &sfc->hclk); in rockchip_sfc_ofdata_to_platdata()
372 ret = clk_enable(&sfc->hclk); in rockchip_sfc_probe()
398 clk_disable(&sfc->hclk); in rockchip_sfc_probe()
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dnvidia,tegra20-car.txt140 109 hclk

12