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Searched refs:ecm (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dlaw.c15 law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; in set_ddr_laws() local
29 ecm->bar = start & 0xfffff000; in set_ddr_laws()
30 ecm->ar = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc)); in set_ddr_laws()
31 debug("DDR:bar=0x%08x\n", ecm->bar); in set_ddr_laws()
32 debug("DDR:ar=0x%08x\n", ecm->ar); in set_ddr_laws()
45 ecm = &immap->sysconf.ddrlaw[1]; in set_ddr_laws()
46 ecm->bar = start & 0xfffff000; in set_ddr_laws()
47 ecm->ar = (LAWAR_EN | (id << 20) | (LAWAR_SIZE & law_sz_enc)); in set_ddr_laws()
48 debug("DDR:bar=0x%08x\n", ecm->bar); in set_ddr_laws()
49 debug("DDR:ar=0x%08x\n", ecm->ar); in set_ddr_laws()
H A Dspd_sdram.c127 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0]; in spd_sdram() local
283 ecm->bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000; in spd_sdram()
284 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); in spd_sdram()
285 debug("DDR:bar=0x%08x\n", ecm->bar); in spd_sdram()
286 debug("DDR:ar=0x%08x\n", ecm->ar); in spd_sdram()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dmp.c334 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); in plat_mp_up() local
341 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); in plat_mp_up()
353 bpcr = in_be32(&ecm->eebpcr); in plat_mp_up()
355 out_be32(&ecm->eebpcr, bpcr); in plat_mp_up()
402 clrbits_be32(&ecm->bptr, 0x80000000); in plat_mp_up()
H A Dcpu_init.c448 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); in cpu_init_f() local
458 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); in cpu_init_f()
/rk3399_rockchip-uboot/board/sbc8548/
H A Dsbc8548.c38 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); in checkboard() local
49 out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ in checkboard()
50 out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ in checkboard()
/rk3399_rockchip-uboot/board/freescale/mpc8544ds/
H A Dmpc8544ds.c30 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); in checkboard() local
50 ecm->eedr = 0xffffffff; /* Clear ecm errors */ in checkboard()
51 ecm->eeer = 0xffffffff; /* Enable ecm errors */ in checkboard()
/rk3399_rockchip-uboot/board/freescale/mpc8548cds/
H A Dmpc8548cds.c33 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); in checkboard() local
56 ecm->eedr = 0xffffffff; /* clear ecm errors */ in checkboard()
57 ecm->eeer = 0xffffffff; /* enable ecm errors */ in checkboard()
/rk3399_rockchip-uboot/board/socrates/
H A Dsocrates.c138 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); in local_bus_init() local
159 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ in local_bus_init()
160 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ in local_bus_init()
/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c35 volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; in fsl_ddr_set_memctl_regs() local
361 setbits_be32(&ecm->eebacr, 0x10000000); in fsl_ddr_set_memctl_regs()
362 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); in fsl_ddr_set_memctl_regs()
520 clrbits_be32(&ecm->eebacr, 10000000); in fsl_ddr_set_memctl_regs()
521 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); in fsl_ddr_set_memctl_regs()