| #
0e00a84c |
| 04-Mar-2018 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
UPSTREAM: libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt header
UPSTREAM: libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel package is installed because tools include libfdt headers from /usr/include/ instead of using internal ones.
This commit moves the header code: include/libfdt.h -> include/linux/libfdt.h include/libfdt_env.h -> include/linux/libfdt_env.h
and replaces include directives: #include <libfdt.h> -> #include <linux/libfdt.h> #include <libfdt_env.h> -> #include <linux/libfdt_env.h>
Change-Id: I6c0f7e50e8b571106627f25ddac008a62bd2994e Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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| #
1fc4e6f4 |
| 25-Nov-2014 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-fdt
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| #
e895a4b0 |
| 24-Oct-2014 |
Simon Glass <sjg@chromium.org> |
fdt: Allow ft_board_setup() to report failure
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detect
fdt: Allow ft_board_setup() to report failure
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected.
Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage.
Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
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| #
f15ea6e1 |
| 10-Dec-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard
Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compul
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard
Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
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| #
77fdd6d1 |
| 02-Dec-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
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| #
5614e71b |
| 30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs.
Signed
Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
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| #
3765b3e7 |
| 07-Oct-2013 |
Wolfgang Denk <wd@denx.de> |
Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
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| #
6612ab33 |
| 21-Aug-2013 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
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| #
997399fa |
| 16-Aug-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc: Fix CamelCase checkpatch warnings
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions. because of this code checkpatch script generates "WARNING: Avoid CamelCas
powerpc: Fix CamelCase checkpatch warnings
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions. because of this code checkpatch script generates "WARNING: Avoid CamelCase".
Convert variables name to normal naming convention and modify board, driver files with updated the new structure.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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| #
326ea986 |
| 31-Jul-2013 |
Stefano Babic <sbabic@denx.de> |
Merge git://git.denx.de/u-boot-arm
Conflicts: board/freescale/mx6qsabrelite/Makefile board/freescale/mx6qsabrelite/mx6qsabrelite.c include/configs/mx6qsabrelite.h
Signed-off-by: Stefano Babic <s
Merge git://git.denx.de/u-boot-arm
Conflicts: board/freescale/mx6qsabrelite/Makefile board/freescale/mx6qsabrelite/mx6qsabrelite.c include/configs/mx6qsabrelite.h
Signed-off-by: Stefano Babic <sbabic@denx.de>
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| #
8b485ba1 |
| 25-Jul-2013 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into u-boot-arm/master
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| #
1a459660 |
| 08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
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| #
fdfa1970 |
| 13-Jan-2012 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: fsl_lbc: add printout of LCRR and LBCR to local bus regs sbc8548: Fix up local bus init to b
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: fsl_lbc: add printout of LCRR and LBCR to local bus regs sbc8548: Fix up local bus init to be frequency aware sbc8548: enable support for hardware SPD errata workaround sbc8548: relocate fixed ddr init code to ddr.c file sbc8548: Make enabling SPD RAM configuration work sbc8548: Fix LBC SDRAM initialization settings sbc8548: enable ability to boot from alternate flash sbc8548: relocate 64MB user flash to sane boundary Revert "SBC8548: fix address mask to allow 64M flash" MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM eXMeritus HWW-1U-1A: Minor environment variable tweaks
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| #
670c24f6 |
| 13-Jan-2012 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx: fsl_lbc: add printout of LCRR and LBCR to local bus regs sbc8548: Fix up local bus init
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx: fsl_lbc: add printout of LCRR and LBCR to local bus regs sbc8548: Fix up local bus init to be frequency aware sbc8548: enable support for hardware SPD errata workaround sbc8548: relocate fixed ddr init code to ddr.c file sbc8548: Make enabling SPD RAM configuration work sbc8548: Fix LBC SDRAM initialization settings sbc8548: enable ability to boot from alternate flash sbc8548: relocate 64MB user flash to sane boundary Revert "SBC8548: fix address mask to allow 64M flash" MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM eXMeritus HWW-1U-1A: Minor environment variable tweaks
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| #
e2b363ff |
| 31-Dec-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
sbc8548: Fix up local bus init to be frequency aware
The code here was copied from the mpc8548cds support, and it wasn't using the CONFIG_SYS_LBC_LCRR define, and was just unconditionally setting th
sbc8548: Fix up local bus init to be frequency aware
The code here was copied from the mpc8548cds support, and it wasn't using the CONFIG_SYS_LBC_LCRR define, and was just unconditionally setting the LCRR_EADC bit. Snooping with a hardware debugger also showed we had LCRR_DBYP set, since we were setting it based on a read of an uninitialized lcrr read via clkdiv. Borrow from the code in the tqm85xx.c support to add LBC frequency aware masking of these bits.
This change will correct reliability issues associated with trying to use the 128MB of LBC 100MHz SDRAM on this board. Thanks to Keith Savage for assistance in diagnosing the root cause of this.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| #
2a6b3b74 |
| 31-Dec-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
sbc8548: relocate fixed ddr init code to ddr.c file
Nothing to see here, just a relocation of the fixed ddr init sequence to live in the actual ddr.c file itself.
Signed-off-by: Paul Gortmaker <pau
sbc8548: relocate fixed ddr init code to ddr.c file
Nothing to see here, just a relocation of the fixed ddr init sequence to live in the actual ddr.c file itself.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| #
5f4c6f0d |
| 31-Dec-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
sbc8548: Fix LBC SDRAM initialization settings
These were cloned from the mpc8548cds platform which has a different memory layout (1/2 the size). Set the values by comparing to the register file fo
sbc8548: Fix LBC SDRAM initialization settings
These were cloned from the mpc8548cds platform which has a different memory layout (1/2 the size). Set the values by comparing to the register file for the board used during JTAG init sequence:
LSDMR1 0x2863B727 /* PCHALL */ LSDMR2 0x0863B727 /* NORMAL */ LSDMR3 0x1863B727 /* MRW */ LSDMR4 0x4063B727 /* RFEN */
This differs from what was there already in that the RFEN is not bundled in all four steps implicitly, but issued once as the final step.
The other difference seen when comparing vs. the register file init, is that since the memory is split across /CS3 and /CS4, the dummy writes need to go to 0xf000_0000 _and_ to 0xf400_0000.
We also rewrite the final LBC SDRAM inits as macros, as there is no real need for them to be a local variable that is modified on the fly at runtime.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| #
f0aec4ea |
| 31-Dec-2011 |
Paul Gortmaker <paul.gortmaker@windriver.com> |
sbc8548: enable ability to boot from alternate flash
This board has an 8MB soldered on flash, and a 64MB SODIMM flash module. Normally the board boots from the 8MB flash, but the hardware can be co
sbc8548: enable ability to boot from alternate flash
This board has an 8MB soldered on flash, and a 64MB SODIMM flash module. Normally the board boots from the 8MB flash, but the hardware can be configured for booting from the 64MB flash as well by swapping CS0 and CS6. This can be handy for recovery purposes, or for supporting u-boot and VxBoot at the same time.
To support this in u-boot, we need to have different BR0/OR0 and BR6/OR6 settings in place for when the board is configured in this way, and a different TEXT_BASE needs to be used due to the larger sector size of the 64MB flash module.
We introduce the suffix _8M and _64M for the BR0/BR6 and the OR0/OR6 values so it is clear which is being used to map what specific device.
The larger sector size (512k) of the alternate flash needs a larger malloc pool, otherwise you'll get failures when running saveenv, so bump it up accordingly.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| #
10d6c696 |
| 16-Nov-2011 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND arch/powerpc/cpu/mpc8xxx/ddr/ctrl_r
Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning drivers/qe/uec.c: Fix GCC 4.6 build warning drivers/usb/host/ehci-fsl.c: Fix GCC 4.6 build warning drivers/net/fm/fm.c: Fix GCC 4.6 build warning board/sbc8560/sbc8560.c: Fix GCC 4.6 build warning board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning board/freescale/common/pixis.c: Fix GCC 4.6 build warning board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning phylib: Enable AR8021 phy support powerpc/85xx: Set max alloc length to 10MB on P1022DS powerpc/mpc85xx: Set SYSCLK to the required frequency powerpc/85xx: Fix NAND SPL support powerpc/85xx: Fix MPC8572DS NAND build fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399 powerpc/85xx: Add support for Book-E MMU Arch v2.0 powerpc/85xx: Make inclusion of USB device fixup conditional powerpc/85xx: Fix warning for USB device-fixup powerpc/85xx: resize the boot page TLB before relocating CCSR powerpc/85xx: verify the current address of CCSR before relocating it powerpc/85xx: add some missing sync instructions in the CCSR relocation code powerpc/85xx: fix some comments in the CCSR relocation code powerpc/85xx: fix definition of MAS register macros powerpc/mpc8548cds: Fix network initialization powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129 powerpc/QorIQ: fix network frame manager TBI PHY address settings
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| #
c7801ee4 |
| 16-Nov-2011 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND arch/powerpc/cpu/mpc8xxx/ddr/ct
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning drivers/qe/uec.c: Fix GCC 4.6 build warning drivers/usb/host/ehci-fsl.c: Fix GCC 4.6 build warning drivers/net/fm/fm.c: Fix GCC 4.6 build warning board/sbc8560/sbc8560.c: Fix GCC 4.6 build warning board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning board/freescale/common/pixis.c: Fix GCC 4.6 build warning board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning phylib: Enable AR8021 phy support powerpc/85xx: Set max alloc length to 10MB on P1022DS powerpc/mpc85xx: Set SYSCLK to the required frequency powerpc/85xx: Fix NAND SPL support powerpc/85xx: Fix MPC8572DS NAND build fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399 powerpc/85xx: Add support for Book-E MMU Arch v2.0 powerpc/85xx: Make inclusion of USB device fixup conditional powerpc/85xx: Fix warning for USB device-fixup powerpc/85xx: resize the boot page TLB before relocating CCSR powerpc/85xx: verify the current address of CCSR before relocating it powerpc/85xx: add some missing sync instructions in the CCSR relocation code powerpc/85xx: fix some comments in the CCSR relocation code powerpc/85xx: fix definition of MAS register macros powerpc/mpc8548cds: Fix network initialization powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129 powerpc/QorIQ: fix network frame manager TBI PHY address settings
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| #
dbe128a9 |
| 09-Nov-2011 |
Kumar Gala <galak@kernel.crashing.org> |
board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning
Fix:
sbc8548.c: In function 'local_bus_init': sbc8548.c:80:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable]
Signed-off-
board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning
Fix:
sbc8548.c: In function 'local_bus_init': sbc8548.c:80:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| #
e1ccf97c |
| 17-Jan-2011 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
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| #
2d0a054d |
| 17-Dec-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code
Remove duplicated code in SBC8548 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs
powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code
Remove duplicated code in SBC8548 board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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| #
70961ba4 |
| 17-Dec-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
mpc85xx: rename sdram_init() lbc_sdram_init()
sdram_init() is used to initialize sdram on the lbc. Rename it accordingly.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kum
mpc85xx: rename sdram_init() lbc_sdram_init()
sdram_init() is used to initialize sdram on the lbc. Rename it accordingly.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| #
38dba0c2 |
| 17-Dec-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I
mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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