| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | dmc_fsp.c | 369 u32 dram_type, os_reg2_val, os_reg3_val; in dmc_fsp_probe() local
385 dram_type = SYS_REG_DEC_DDRTYPE_V3(os_reg2_val, os_reg3_val); in dmc_fsp_probe()
387 if (dram_type == DDR2) in dmc_fsp_probe()
389 else if (dram_type == DDR3) in dmc_fsp_probe()
391 else if (dram_type == DDR4) in dmc_fsp_probe()
393 else if (dram_type == LPDDR2) in dmc_fsp_probe()
395 else if (dram_type == LPDDR3) in dmc_fsp_probe()
397 else if (dram_type == LPDDR4) in dmc_fsp_probe()
399 else if (dram_type == LPDDR4X) in dmc_fsp_probe()
401 else if (dram_type == LPDDR5) in dmc_fsp_probe()
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| H A D | sdram_common.c | 131 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type) in sdram_get_cs_cap() argument
136 if (dram_type == DDR4) in sdram_get_cs_cap()
345 int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type) in sdram_detect_dbw() argument
350 if (dram_type == DDR3) { in sdram_detect_dbw()
355 } else if (dram_type == LPDDR4) { in sdram_detect_dbw()
357 } else if (dram_type == LPDDR3 || dram_type == LPDDR2) { in sdram_detect_dbw()
528 int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type) in sdram_detect_cs1_row() argument
536 cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type); in sdram_detect_cs1_row()
538 if (dram_type == DDR4) { in sdram_detect_cs1_row()
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| H A D | sdram_px30.c | 506 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap() local
508 if (dram_type != DDR4) { in dram_detect_cap()
512 if (dram_type == LPDDR2) in dram_detect_cap()
520 sdram_detect_dbw(cap_info, dram_type); in dram_detect_cap()
542 if (data_training(dram, 1, dram_type) == 0) in dram_detect_cap()
549 if (data_training(dram, 0, dram_type) == 0) in dram_detect_cap()
573 u32 dram_type = sdram_params->base.dramtype; in get_ddr_param() local
576 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type); in get_ddr_param()
577 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type); in get_ddr_param()
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| H A D | sdram_phy_px30.c | 51 u32 dram_type) in sdram_phy_set_ds_odt() argument
56 if (dram_type == DDR3) { in sdram_phy_set_ds_odt()
65 if (dram_type == LPDDR2) in sdram_phy_set_ds_odt()
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| H A D | sdram_rv1126.c | 2331 u32 dram_type = sdram_params->base.dramtype; in dram_all_config() local
2344 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type); in dram_all_config()
2345 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type); in dram_all_config()
2395 u32 dram_type = sdram_params->base.dramtype; in ddr_set_atags() local
2405 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type); in ddr_set_atags()
2406 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type); in ddr_set_atags()
2722 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap() local
2727 if (dram_type != LPDDR4 && dram_type != LPDDR4X) { in dram_detect_cap()
2728 if (dram_type != DDR4) { in dram_detect_cap()
2729 if (dram_type == DDR3) in dram_detect_cap()
[all …]
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| H A D | sdram_rk3328.c | 421 u32 dram_type = sdram_params->base.dramtype; in dram_detect_cap() local
423 if (dram_type != DDR4) { in dram_detect_cap()
432 sdram_detect_dbw(cap_info, dram_type); in dram_detect_cap()
454 if (data_training(dram, 1, dram_type) == 0) in dram_detect_cap()
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| H A D | sdram_pctl_px30.c | 154 u32 dram_type) in pctl_remodify_sdram_params() argument
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun9i.c | 99 u32 dram_type; member
462 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
575 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
595 writel(MCTL_MSTR_DEVICETYPE(para->dram_type) | in mctl_channel_init()
596 MCTL_MSTR_BURSTLENGTH(para->dram_type) | in mctl_channel_init()
601 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
632 if (para->dram_type != DRAM_TYPE_DDR3) in mctl_channel_init()
666 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
720 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
752 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
[all …]
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| H A D | dram_sun8i_a83t.c | 28 u8 dram_type; member
38 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | in mctl_set_cr()
134 if (para->dram_type == DRAM_TYPE_DDR3) { in auto_set_timing_para()
139 } else if (para->dram_type == DRAM_TYPE_LPDDR3) { in auto_set_timing_para()
324 if (para->dram_type == DRAM_TYPE_LPDDR3) in mctl_channel_init()
338 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
444 para.dram_type = CONFIG_DRAM_TYPE; in sunxi_dram_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 29 u32 dbw, dram_type; in rockchip_sdram_size() local
35 dram_type = (sys_reg >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; in rockchip_sdram_size()
82 if (dram_type == DDR4) { in rockchip_sdram_size()
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| /rk3399_rockchip-uboot/arch/x86/include/asm/arch-baytrail/fsp/ |
| H A D | fsp_vpd.h | 14 uint8_t dram_type; member
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_common.h | 437 int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type);
443 int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type);
448 u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type);
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| H A D | sdram_pctl_px30.h | 264 u32 dram_type);
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| /rk3399_rockchip-uboot/arch/x86/cpu/baytrail/ |
| H A D | fsp_configs.c | 232 mem->dram_type = fdtdec_get_int(blob, node, in update_fsp_configs()
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