13a1a18ffSSimon Glass /* 23a1a18ffSSimon Glass * Copyright (C) 2013, Intel Corporation 33a1a18ffSSimon Glass * Copyright (C) 2015 Google, Inc 43a1a18ffSSimon Glass * 53a1a18ffSSimon Glass * SPDX-License-Identifier: Intel 63a1a18ffSSimon Glass */ 73a1a18ffSSimon Glass 83a1a18ffSSimon Glass #ifndef __FSP_VPD_H 93a1a18ffSSimon Glass #define __FSP_VPD_H 103a1a18ffSSimon Glass 113a1a18ffSSimon Glass struct memory_down_data { 123a1a18ffSSimon Glass uint8_t enable_memory_down; 133a1a18ffSSimon Glass uint8_t dram_speed; 143a1a18ffSSimon Glass uint8_t dram_type; 153a1a18ffSSimon Glass uint8_t dimm_0_enable; 163a1a18ffSSimon Glass uint8_t dimm_1_enable; 173a1a18ffSSimon Glass uint8_t dimm_width; 183a1a18ffSSimon Glass uint8_t dimm_density; 193a1a18ffSSimon Glass uint8_t dimm_bus_width; 203a1a18ffSSimon Glass uint8_t dimm_sides; /* Ranks Per dimm_ */ 213a1a18ffSSimon Glass uint8_t dimm_tcl; /* tCL */ 223a1a18ffSSimon Glass /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ 233a1a18ffSSimon Glass uint8_t dimm_trpt_rcd; 243a1a18ffSSimon Glass uint8_t dimm_twr; /* tWR in DRAM clk */ 253a1a18ffSSimon Glass uint8_t dimm_twtr; /* tWTR in DRAM clk */ 263a1a18ffSSimon Glass uint8_t dimm_trrd; /* tRRD in DRAM clk */ 273a1a18ffSSimon Glass uint8_t dimm_trtp; /* tRTP in DRAM clk */ 283a1a18ffSSimon Glass uint8_t dimm_tfaw; /* tFAW in DRAM clk */ 293a1a18ffSSimon Glass }; 303a1a18ffSSimon Glass 313a1a18ffSSimon Glass struct __packed upd_region { 323a1a18ffSSimon Glass uint64_t signature; /* Offset 0x0000 */ 333a1a18ffSSimon Glass uint8_t reserved0[24]; /* Offset 0x0008 */ 343a1a18ffSSimon Glass uint16_t mrc_init_tseg_size; /* Offset 0x0020 */ 353a1a18ffSSimon Glass uint16_t mrc_init_mmio_size; /* Offset 0x0022 */ 363a1a18ffSSimon Glass uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */ 373a1a18ffSSimon Glass uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */ 383a1a18ffSSimon Glass uint8_t emmc_boot_mode; /* Offset 0x0026 */ 393a1a18ffSSimon Glass uint8_t enable_sdio; /* Offset 0x0027 */ 403a1a18ffSSimon Glass uint8_t enable_sdcard; /* Offset 0x0028 */ 413a1a18ffSSimon Glass uint8_t enable_hsuart0; /* Offset 0x0029 */ 423a1a18ffSSimon Glass uint8_t enable_hsuart1; /* Offset 0x002a */ 433a1a18ffSSimon Glass uint8_t enable_spi; /* Offset 0x002b */ 443a1a18ffSSimon Glass uint8_t reserved1; /* Offset 0x002c */ 453a1a18ffSSimon Glass uint8_t enable_sata; /* Offset 0x002d */ 463a1a18ffSSimon Glass uint8_t sata_mode; /* Offset 0x002e */ 473a1a18ffSSimon Glass uint8_t enable_azalia; /* Offset 0x002f */ 483a1a18ffSSimon Glass uint32_t azalia_config_ptr; /* Offset 0x0030 */ 493a1a18ffSSimon Glass uint8_t enable_xhci; /* Offset 0x0034 */ 50*f8f291b0SBin Meng uint8_t lpe_mode; /* Offset 0x0035 */ 51*f8f291b0SBin Meng uint8_t lpss_sio_mode; /* Offset 0x0036 */ 523a1a18ffSSimon Glass uint8_t enable_dma0; /* Offset 0x0037 */ 533a1a18ffSSimon Glass uint8_t enable_dma1; /* Offset 0x0038 */ 543a1a18ffSSimon Glass uint8_t enable_i2_c0; /* Offset 0x0039 */ 553a1a18ffSSimon Glass uint8_t enable_i2_c1; /* Offset 0x003a */ 563a1a18ffSSimon Glass uint8_t enable_i2_c2; /* Offset 0x003b */ 573a1a18ffSSimon Glass uint8_t enable_i2_c3; /* Offset 0x003c */ 583a1a18ffSSimon Glass uint8_t enable_i2_c4; /* Offset 0x003d */ 593a1a18ffSSimon Glass uint8_t enable_i2_c5; /* Offset 0x003e */ 603a1a18ffSSimon Glass uint8_t enable_i2_c6; /* Offset 0x003f */ 613a1a18ffSSimon Glass uint8_t enable_pwm0; /* Offset 0x0040 */ 623a1a18ffSSimon Glass uint8_t enable_pwm1; /* Offset 0x0041 */ 633a1a18ffSSimon Glass uint8_t enable_hsi; /* Offset 0x0042 */ 643a1a18ffSSimon Glass uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */ 653a1a18ffSSimon Glass uint8_t aperture_size; /* Offset 0x0044 */ 663a1a18ffSSimon Glass uint8_t gtt_size; /* Offset 0x0045 */ 676702488cSBin Meng uint8_t reserved2[5]; /* Offset 0x0046 */ 683a1a18ffSSimon Glass uint8_t mrc_debug_msg; /* Offset 0x004b */ 693a1a18ffSSimon Glass uint8_t isp_enable; /* Offset 0x004c */ 70*f8f291b0SBin Meng uint8_t scc_mode; /* Offset 0x004d */ 713a1a18ffSSimon Glass uint8_t igd_render_standby; /* Offset 0x004e */ 723a1a18ffSSimon Glass uint8_t txe_uma_enable; /* Offset 0x004f */ 733a1a18ffSSimon Glass uint8_t os_selection; /* Offset 0x0050 */ 743a1a18ffSSimon Glass uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */ 753a1a18ffSSimon Glass uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */ 763a1a18ffSSimon Glass uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */ 773e79a4abSBin Meng uint8_t enable_igd; /* Offset 0x0054 */ 783e79a4abSBin Meng uint8_t unused_upd_space1[155]; /* Offset 0x0055 */ 793a1a18ffSSimon Glass struct memory_down_data memory_params; /* Offset 0x00f0 */ 803a1a18ffSSimon Glass uint16_t terminator; /* Offset 0x0100 */ 813a1a18ffSSimon Glass }; 823a1a18ffSSimon Glass 833a1a18ffSSimon Glass #define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */ 843a1a18ffSSimon Glass 853a1a18ffSSimon Glass struct __packed vpd_region { 863a1a18ffSSimon Glass uint64_t sign; /* Offset 0x0000 */ 873a1a18ffSSimon Glass uint32_t img_rev; /* Offset 0x0008 */ 883a1a18ffSSimon Glass uint32_t upd_offset; /* Offset 0x000c */ 893a1a18ffSSimon Glass uint8_t unused[16]; /* Offset 0x0010 */ 903a1a18ffSSimon Glass uint32_t fsp_res_memlen; /* Offset 0x0020 */ 913a1a18ffSSimon Glass uint8_t platform_type; /* Offset 0x0024 */ 923a1a18ffSSimon Glass uint8_t enable_secure_boot; /* Offset 0x0025 */ 933a1a18ffSSimon Glass }; 943a1a18ffSSimon Glass #endif 95