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Searched refs:div_shift (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3528.c1051 u32 div_mask, div_shift; in rk3528_dclk_vop_get_clk() local
1063 div_shift = DCLK_VOP_SRC0_DIV_SHIFT; in rk3528_dclk_vop_get_clk()
1071 div_shift = DCLK_VOP_SRC1_DIV_SHIFT; in rk3528_dclk_vop_get_clk()
1079 div = (con & div_mask) >> div_shift; in rk3528_dclk_vop_get_clk()
1093 u32 div_mask, div_shift; in rk3528_dclk_vop_set_clk() local
1105 div_shift = DCLK_VOP_SRC0_DIV_SHIFT; in rk3528_dclk_vop_set_clk()
1113 div_shift = DCLK_VOP_SRC1_DIV_SHIFT; in rk3528_dclk_vop_set_clk()
1128 div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask; in rk3528_dclk_vop_set_clk()
1137 u32 sel_shift, sel_mask, div_shift, div_mask; in rk3528_uart_get_rate() local
1146 div_shift = CLK_UART0_SRC_DIV_SHIFT; in rk3528_uart_get_rate()
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H A Dclk_rk3399.c670 uint8_t div_shift; member
682 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
685 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
688 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
691 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
694 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
714 div = bitfield_extract(val, spiclk->div_shift, in rk3399_spi_get_clk()
739 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) | in rk3399_spi_set_clk()
741 ((src_clk_div << spiclk->div_shift) | in rk3399_spi_set_clk()
H A Dclk_rk3368.c496 uint8_t div_shift; member
504 [0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
505 [1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
506 [2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
530 div = extract_bits(val, 7, spiclk->div_shift); in rk3368_spi_get_clk()
555 ((0x7f << spiclk->div_shift) | in rk3368_spi_set_clk()
557 ((src_clk_div << spiclk->div_shift) | in rk3368_spi_set_clk()
H A Dclk_rk3576.c1178 u32 mask, div_shift, sel_shift; in rk3576_dclk_vop_set_clk() local
1187 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_set_clk()
1196 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_set_clk()
1205 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3576_dclk_vop_set_clk()
1220 ((div - 1) << div_shift)); in rk3576_dclk_vop_set_clk()
1228 ((div - 1) << div_shift)); in rk3576_dclk_vop_set_clk()
1274 (best_div - 1) << div_shift); in rk3576_dclk_vop_set_clk()
1320 u32 mask, div_shift, sel_shift; in rk3576_clk_csihost_set_clk() local
1326 div_shift = CLK_DSIHOST0_DIV_SHIFT; in rk3576_clk_csihost_set_clk()
1373 (best_div - 1) << div_shift); in rk3576_clk_csihost_set_clk()
H A Dclk_rk3588.c1115 u32 mask, div_shift, sel_shift; in rk3588_dclk_vop_set_clk() local
1124 div_shift = DCLK0_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1133 div_shift = DCLK1_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1142 div_shift = DCLK2_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1150 div_shift = DCLK3_VOP_SRC_DIV_SHIFT; in rk3588_dclk_vop_set_clk()
1165 ((div - 1) << div_shift)); in rk3588_dclk_vop_set_clk()
1173 ((div - 1) << div_shift)); in rk3588_dclk_vop_set_clk()
1214 (best_div - 1) << div_shift); in rk3588_dclk_vop_set_clk()