| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rv1108_pctl_phy.c | 116 if (params_priv->ddr_config_t.ddr_type == DDR3 || in memory_init()
117 params_priv->ddr_config_t.ddr_type == DDR2) { in memory_init()
139 if (params_priv->ddr_config_t.ddr_type == DDR3) { in memory_init()
294 if (params_priv->ddr_config_t.ddr_type == DDR3 || in pctl_cfg()
295 params_priv->ddr_config_t.ddr_type == DDR2) { in pctl_cfg()
305 if (params_priv->ddr_config_t.ddr_type == DDR3) in pctl_cfg()
380 switch (params_priv->ddr_config_t.ddr_type) { in phy_cfg()
480 if (params_priv->ddr_config_t.ddr_type == DDR3) { in sdram_detect()
539 os_reg = (params_priv->ddr_config_t.ddr_type & SYS_REG_DDRTYPE_MASK) << in sdram_all_config()
570 switch (params_priv->ddr_config_t.ddr_type & SYS_REG_DDRTYPE_MASK) { in sdram_all_config()
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| H A D | sdram_rk3308.c | 454 if (params_priv->ddr_config_t.ddr_type == DDR3 || in pctl_cfg_grf()
455 params_priv->ddr_config_t.ddr_type == DDR2) in pctl_cfg_grf()
527 if (params_priv->ddr_config_t.ddr_type == LPDDR2) { in set_ds_odt()
698 switch (params_priv->ddr_config_t.ddr_type) { in modify_sdram_params()
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| /rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_init.c | 86 static char *ddr_type = "DDR3"; variable
192 ddr_type); in ddr3_restore_and_set_final_windows()
334 printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type); in ddr3_init()
394 printf("%s Training Sequence - FAILED\n", ddr_type); in ddr3_init()
417 printf("%s Training Sequence - Ended Successfully\n", ddr_type); in ddr3_init()
764 printf("%s Training Sequence - FAILED\n", ddr_type); in ddr3_hws_tune_training_params()
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| /rk3399_rockchip-uboot/board/rockchip/evb_rk3036/ |
| H A D | evb_rk3036.c | 18 config->ddr_type = 3; in get_ddr_config()
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| /rk3399_rockchip-uboot/board/rockchip/kylin_rk3036/ |
| H A D | kylin_rk3036.c | 19 config->ddr_type = 3; in get_ddr_config()
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| /rk3399_rockchip-uboot/cmd/ddr_tool/ddr_dq_eye/ |
| H A D | ddr_dq_eye.c | 173 u32 ddr_type; in do_ddr_dq_eye() local
188 ddr_type = (readl(0xfe020208) >> 13) & 0x7; in do_ddr_dq_eye()
190 ddr_type = ((readl(0xfdc2020c) & (0x3 << 12)) >> 9) | in do_ddr_dq_eye()
232 switch (ddr_type) { in do_ddr_dq_eye()
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rk3308/ |
| H A D | sdram-rk3308-ddr2-detect-393.inc | 7 .ddr_type = 0x2,
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| H A D | sdram-rk3308-ddr3-detect-393.inc | 7 .ddr_type = 0x3,
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| H A D | sdram-rk3308-lpddr2-detect-393.inc | 7 .ddr_type = 0x5,
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| H A D | sdram-rk3308-ddr3-detect-589.inc | 7 .ddr_type = 0x3,
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| H A D | sdram-rk3308-lpddr2-detect-451.inc | 7 .ddr_type = 0x5,
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| H A D | sdram-rk3308-ddr3-detect-451.inc | 7 .ddr_type = 0x3,
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| H A D | sdram-rk3308-ddr2-detect-451.inc | 7 .ddr_type = 0x2,
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| /rk3399_rockchip-uboot/board/ccv/xpress/ |
| H A D | spl.c | 62 .ddr_type = DDR_TYPE_DDR3,
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| /rk3399_rockchip-uboot/board/barco/platinum/ |
| H A D | spl_picon.c | 140 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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| H A D | spl_titanium.c | 143 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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| /rk3399_rockchip-uboot/arch/x86/include/asm/ |
| H A D | global_data.h | 24 uint16_t ddr_type; member
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| /rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/ |
| H A D | mrc.h | 115 uint8_t ddr_type; /* DDR3, DDR3L */ member
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| /rk3399_rockchip-uboot/board/engicam/common/ |
| H A D | spl.c | 190 .ddr_type = DDR_TYPE_DDR3,
302 .ddr_type = DDR_TYPE_DDR3,
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| /rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/ |
| H A D | litesom.c | 130 .ddr_type = DDR_TYPE_DDR3,
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| H A D | opos6ul.c | 227 .ddr_type = DDR_TYPE_DDR3,
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| /rk3399_rockchip-uboot/board/liebherr/display5/ |
| H A D | spl.c | 137 .ddr_type = DDR_TYPE_DDR3, in spl_dram_init()
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| /rk3399_rockchip-uboot/arch/x86/cpu/quark/ |
| H A D | dram.c | 82 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0); in mrc_configure_params()
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| /rk3399_rockchip-uboot/board/freescale/mx6ul_14x14_evk/ |
| H A D | mx6ul_14x14_evk.c | 768 .ddr_type = DDR_TYPE_LPDDR2,
808 .ddr_type = DDR_TYPE_DDR3,
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_rk3036.h | 320 u32 ddr_type; member
|