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/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar934x/
H A Dddr.c43 u32 reg, cycle, ctl; in ar934x_ddr_init() local
52 cycle = 0xffff; in ar934x_ddr_init()
58 cycle = 0xff; in ar934x_ddr_init()
60 cycle = 0xffff; in ar934x_ddr_init()
64 cycle = 0xffff; /* DDR2 16bit */ in ar934x_ddr_init()
81 cycle = 0xffffffff; in ar934x_ddr_init()
148 writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); in ar934x_ddr_init()
/rk3399_rockchip-uboot/drivers/pwm/
H A DKconfig6 control over the duty cycle (high and low time) of the signal. This
17 supports a programmable period and duty cycle. A 32-bit counter is
26 programmable period and duty cycle. A 32-bit counter is used.
43 four channels with a programmable period and duty cycle. Only a
44 32KHz clock is supported by the driver but the duty cycle is
/rk3399_rockchip-uboot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg40 # bit4: 0, addr/cmd in same cycle
57 # bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
58 # bit7-4: 4, 5 cycle tRCD
62 # bit20: 0, 16 cycle tRAS (tRAS[4])
64 # bit27-24: 3, 4 cycle tRRD
69 # bit6-0: 0x23, 35 cycle tRFC
70 # bit8-7: 0, 1 cycle tR2R
132 # bit9: 0, no half clock cycle addition to dataout
133 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
134 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
H A Dkwbimage-lsxhl.cfg57 # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
58 # bit7-4: 4, 5 cycle tRCD
62 # bit20: 1, 18 cycle tRAS (tRAS[4])
64 # bit27-24: 2, 3 cycle tRRD
69 # bit6-0: 0x32, 50 cycle tRFC
70 # bit8-7: 0, 1 cycle tR2R
132 # bit9: 0, no half clock cycle addition to dataout
133 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
134 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/d-link/dns325/
H A Dkwbimage.cfg38 # bit4: 0, addr/cmd in smame cycle
54 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
55 # bit7-4: 5, 6 cycle tRCD
59 # bit20: 1, 18 cycle tRAS (tRAS[4])
61 # bit27-24: 2, 3 cycle tRRD
65 # bit6-0: 0x33, 33 cycle tRFC
66 # bit8-7: 0, 1 cycle tR2R
122 # bit9: 0, no half clock cycle addition to dataout
123 # bit10: 0, 1/4 clock cycle skew enabled for addr/ctl signals
124 # bit11: 0, 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/atmel/at91sam9261ek/
H A Dat91sam9261ek.c56 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
65 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
104 &smc->cs[2].cycle); in at91sam9261ek_dm9000_hw_init()
118 &smc->cs[2].cycle); in at91sam9261ek_dm9000_hw_init()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Domap-gpmc-smsc9221.dtsi42 gpmc,rd-cycle-ns = <60>;
43 gpmc,wr-cycle-ns = <54>;
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Dintel-gma.txt15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
33 intel,panel-power-cycle-delay = <6>;
/rk3399_rockchip-uboot/board/Seagate/nas220/
H A Dkwbimage.cfg36 # bit 4: 0=addr/cmd in smame cycle
116 # bit9 : 0 , no half clock cycle addition to dataout
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/drivers/input/
H A Drockchip_ir.c215 u32 cycle_hpr, cycle_lpr, cycle; in rockchip_ir_irq() local
223 cycle = cycle_hpr; in rockchip_ir_irq()
226 cycle = cycle_lpr; in rockchip_ir_irq()
232 ev.duration = cycle * priv->period; in rockchip_ir_irq()
/rk3399_rockchip-uboot/board/Marvell/guruplug/
H A Dkwbimage.cfg33 # bit 4: 0=addr/cmd in smame cycle
112 # bit9 : 0 , no half clock cycle addition to dataout
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Seagate/dockstar/
H A Dkwbimage.cfg36 # bit 4: 0=addr/cmd in smame cycle
115 # bit9 : 0 , no half clock cycle addition to dataout
116 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
117 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Synology/ds109/
H A Dkwbimage.cfg37 # bit 4: 0=addr/cmd in smame cycle
116 # bit9 : 0 , no half clock cycle addition to dataout
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Marvell/dreamplug/
H A Dkwbimage.cfg34 # bit 4: 0=addr/cmd in smame cycle
113 # bit9 : 0 , no half clock cycle addition to dataout
114 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
115 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Seagate/goflexhome/
H A Dkwbimage.cfg39 # bit 4: 0=addr/cmd in smame cycle
118 # bit9 : 0 , no half clock cycle addition to dataout
119 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
120 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Marvell/sheevaplug/
H A Dkwbimage.cfg33 # bit 4: 0=addr/cmd in smame cycle
112 # bit9 : 0 , no half clock cycle addition to dataout
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/keymile/km_arm/
H A Dkwbimage-memphis.cfg57 # bit 4: 0=addr/cmd in smame cycle
127 # bit9 : 0 , no half clock cycle addition to dataout
128 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
129 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
142 # bit3-0 : 0001, M_ODT assertion same cycle as write
H A Dkwbimage.cfg54 # bit 4: 0=addr/cmd in smame cycle
124 # bit9 : 0 , no half clock cycle addition to dataout
125 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
126 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/LaCie/netspace_v2/
H A Dkwbimage.cfg34 # bit 4: 0=addr/cmd in smame cycle
112 # bit9 : 0 , no half clock cycle addition to dataout
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
H A Dkwbimage-is2.cfg34 # bit 4: 0=addr/cmd in smame cycle
112 # bit9 : 0 , no half clock cycle addition to dataout
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
H A Dkwbimage-ns2l.cfg34 # bit 4: 0=addr/cmd in smame cycle
112 # bit9 : 0 , no half clock cycle addition to dataout
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/cloudengines/pogo_e02/
H A Dkwbimage.cfg37 # bit 4: 0=addr/cmd in smame cycle
116 # bit9 : 0 , no half clock cycle addition to dataout
117 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
118 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/raidsonic/ib62x0/
H A Dkwbimage.cfg34 # bit4: 0x0, addr/cmd in smame cycle
113 # bit9: 0x0, no half clock cycle addition to dataout
114 # bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
115 # bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/LaCie/net2big_v2/
H A Dkwbimage.cfg34 # bit 4: 0=addr/cmd in smame cycle
112 # bit9 : 0 , no half clock cycle addition to dataout
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
/rk3399_rockchip-uboot/board/Marvell/openrd/
H A Dkwbimage.cfg33 # bit 4: 0=addr/cmd in smame cycle
112 # bit9 : 0 , no half clock cycle addition to dataout
113 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
114 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh

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