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Searched refs:chan (Results 1 – 25 of 47) sorted by relevance

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/rk3399_rockchip-uboot/drivers/ddr/marvell/axp/
H A Dxor.c21 static int mv_xor_cmd_set(u32 chan, int command);
22 static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
141 static int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl) in mv_xor_ctrl_set() argument
146 val = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) in mv_xor_ctrl_set()
150 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
155 int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high, in mv_xor_mem_init() argument
161 if (chan >= MV_XOR_MAX_CHAN) in mv_xor_mem_init()
164 if (MV_ACTIVE == mv_xor_state_get(chan)) in mv_xor_mem_init()
172 tmp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
175 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), tmp); in mv_xor_mem_init()
[all …]
H A Dxor_regs.h14 #define XOR_UNIT(chan) ((chan) >> 1) argument
15 #define XOR_CHAN(chan) ((chan) & 1) argument
22 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x10 + ((chan) * 4))) argument
23 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x20 + ((chan) * 4))) argument
32 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x200 + ((chan) * 4))) argument
33 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x210 + ((chan) * 4))) argument
34 #define XOR_BYTE_COUNT_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x220 + ((chan) * 4))) argument
36 #define XOR_DST_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2B0 + ((chan) * 4))) argument
37 #define XOR_BLOCK_SIZE_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x2C0 + ((chan) * 4))) argument
97 #define XOR_WINDOW_CTRL_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + (0x240 + ((chan) * 4))) argument
H A Dxor.h64 int mv_xor_state_get(u32 chan);
67 int mv_xor_transfer(u32 chan, int xor_type, u32 xor_chain_ptr);
68 int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, u32 init_val_high,
/rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/
H A Dxor.c143 int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl) in mv_xor_ctrl_set() argument
148 old_value = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))) & in mv_xor_ctrl_set()
152 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), xor_ctrl); in mv_xor_ctrl_set()
157 int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, in mv_xor_mem_init() argument
163 if (chan >= MV_XOR_MAX_CHAN) in mv_xor_mem_init()
166 if (MV_ACTIVE == mv_xor_state_get(chan)) in mv_xor_mem_init()
174 temp = reg_read(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan))); in mv_xor_mem_init()
177 reg_write(XOR_CONFIG_REG(XOR_UNIT(chan), XOR_CHAN(chan)), temp); in mv_xor_mem_init()
183 reg_write(XOR_DST_PTR_REG(XOR_UNIT(chan), XOR_CHAN(chan)), start_ptr); in mv_xor_mem_init()
189 reg_write(XOR_BLOCK_SIZE_REG(XOR_UNIT(chan), XOR_CHAN(chan)), in mv_xor_mem_init()
[all …]
H A Dxor_regs.h14 #define XOR_UNIT(chan) ((chan) >> 1) argument
15 #define XOR_CHAN(chan) ((chan) & 1) argument
22 #define XOR_CONFIG_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
23 (0x10 + ((chan) * 4)))
24 #define XOR_ACTIVATION_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
25 (0x20 + ((chan) * 4)))
34 #define XOR_NEXT_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
35 (0x200 + ((chan) * 4)))
36 #define XOR_CURR_DESC_PTR_REG(unit, chan) (MV_XOR_REGS_BASE(unit) + \ argument
37 (0x210 + ((chan) * 4)))
[all …]
H A Dxor.h85 enum mv_state mv_xor_state_get(u32 chan);
87 int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl);
88 int mv_xor_command_set(u32 chan, enum mv_command command);
89 int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num,
/rk3399_rockchip-uboot/drivers/mailbox/
H A Dmailbox-uclass.c19 static int mbox_of_xlate_default(struct mbox_chan *chan, in mbox_of_xlate_default() argument
22 debug("%s(chan=%p)\n", __func__, chan); in mbox_of_xlate_default()
29 chan->id = args->args[0]; in mbox_of_xlate_default()
34 int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan) in mbox_get_by_index() argument
41 debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan); in mbox_get_by_index()
59 chan->dev = dev_mbox; in mbox_get_by_index()
61 ret = ops->of_xlate(chan, &args); in mbox_get_by_index()
63 ret = mbox_of_xlate_default(chan, &args); in mbox_get_by_index()
69 ret = ops->request(chan); in mbox_get_by_index()
79 struct mbox_chan *chan) in mbox_get_by_name() argument
[all …]
H A Dsandbox-mbox.c24 static int sandbox_mbox_request(struct mbox_chan *chan) in sandbox_mbox_request() argument
26 debug("%s(chan=%p)\n", __func__, chan); in sandbox_mbox_request()
28 if (chan->id >= SANDBOX_MBOX_CHANNELS) in sandbox_mbox_request()
34 static int sandbox_mbox_free(struct mbox_chan *chan) in sandbox_mbox_free() argument
36 debug("%s(chan=%p)\n", __func__, chan); in sandbox_mbox_free()
41 static int sandbox_mbox_send(struct mbox_chan *chan, const void *data) in sandbox_mbox_send() argument
43 struct sandbox_mbox *sbm = dev_get_priv(chan->dev); in sandbox_mbox_send()
46 debug("%s(chan=%p, data=%p)\n", __func__, chan, data); in sandbox_mbox_send()
48 sbm->chans[chan->id].rx_msg = *pmsg ^ SANDBOX_MBOX_PING_XOR; in sandbox_mbox_send()
49 sbm->chans[chan->id].rx_msg_valid = true; in sandbox_mbox_send()
[all …]
H A Dtegra-hsp.c74 static int tegra_hsp_of_xlate(struct mbox_chan *chan, in tegra_hsp_of_xlate() argument
77 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_of_xlate()
84 chan->id = (args->args[0] << 16) | args->args[1]; in tegra_hsp_of_xlate()
89 static int tegra_hsp_request(struct mbox_chan *chan) in tegra_hsp_request() argument
93 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_request()
95 db_id = tegra_hsp_db_id(chan->id); in tegra_hsp_request()
104 static int tegra_hsp_free(struct mbox_chan *chan) in tegra_hsp_free() argument
106 debug("%s(chan=%p)\n", __func__, chan); in tegra_hsp_free()
111 static int tegra_hsp_send(struct mbox_chan *chan, const void *data) in tegra_hsp_send() argument
113 struct tegra_hsp *thsp = dev_get_priv(chan->dev); in tegra_hsp_send()
[all …]
H A Dsandbox-mbox-test.c13 struct mbox_chan chan; member
20 return mbox_get_by_name(dev, "test", &sbmt->chan); in sandbox_mbox_test_get()
27 return mbox_send(&sbmt->chan, &msg); in sandbox_mbox_test_send()
34 return mbox_recv(&sbmt->chan, msg, 100); in sandbox_mbox_test_recv()
41 return mbox_free(&sbmt->chan); in sandbox_mbox_test_free()
/rk3399_rockchip-uboot/drivers/pwm/
H A Dsandbox_pwm.c28 struct sandbox_pwm_chan chan[NUM_CHANNELS]; member
35 struct sandbox_pwm_chan *chan; in sandbox_pwm_set_config() local
39 chan = &priv->chan[channel]; in sandbox_pwm_set_config()
40 chan->period_ns = period_ns; in sandbox_pwm_set_config()
41 chan->duty_ns = duty_ns; in sandbox_pwm_set_config()
50 struct sandbox_pwm_chan *chan; in sandbox_pwm_set_enable() local
54 chan = &priv->chan[channel]; in sandbox_pwm_set_enable()
55 chan->enable = enable; in sandbox_pwm_set_enable()
64 struct sandbox_pwm_chan *chan; in sandbox_pwm_set_invert() local
68 chan = &priv->chan[channel]; in sandbox_pwm_set_invert()
[all …]
/rk3399_rockchip-uboot/drivers/firmware/scmi/
H A Dmailbox_agent.c34 struct scmi_mbox_channel *chan = dev_get_priv(dev); in scmi_mbox_process_msg() local
37 ret = scmi_write_msg_to_smt(dev, &chan->smt, msg); in scmi_mbox_process_msg()
42 ret = mbox_send(&chan->mbox, chan->smt.buf); in scmi_mbox_process_msg()
49 ret = mbox_recv(&chan->mbox, chan->smt.buf, chan->timeout_us); in scmi_mbox_process_msg()
55 ret = scmi_read_resp_from_smt(dev, &chan->smt, msg); in scmi_mbox_process_msg()
58 scmi_clear_smt_channel(&chan->smt); in scmi_mbox_process_msg()
65 struct scmi_mbox_channel *chan = dev_get_priv(dev); in scmi_mbox_probe() local
68 chan->timeout_us = TIMEOUT_US_10MS; in scmi_mbox_probe()
70 ret = mbox_get_by_index(dev, 0, &chan->mbox); in scmi_mbox_probe()
76 ret = scmi_dt_get_smt_buffer(dev, &chan->smt); in scmi_mbox_probe()
[all …]
H A Dsmccc_agent.c33 struct scmi_smccc_channel *chan = dev_get_priv(dev); in scmi_smccc_process_msg() local
37 ret = scmi_write_msg_to_smt(dev, &chan->smt, msg); in scmi_smccc_process_msg()
41 arm_smccc_smc(chan->func_id, 0, 0, 0, 0, 0, 0, 0, &res); in scmi_smccc_process_msg()
45 ret = scmi_read_resp_from_smt(dev, &chan->smt, msg); in scmi_smccc_process_msg()
47 scmi_clear_smt_channel(&chan->smt); in scmi_smccc_process_msg()
54 struct scmi_smccc_channel *chan = dev_get_priv(dev); in scmi_smccc_probe() local
64 chan->func_id = func_id; in scmi_smccc_probe()
66 ret = scmi_dt_get_smt_buffer(dev, &chan->smt); in scmi_smccc_probe()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk3399.c38 struct chan_info chan[2]; member
139 static void set_memory_map(const struct chan_info *chan, u32 channel, in set_memory_map() argument
144 u32 *denali_ctl = chan->pctl->denali_ctl; in set_memory_map()
145 u32 *denali_pi = chan->pi->denali_pi; in set_memory_map()
195 static void phy_io_config(const struct chan_info *chan, in phy_io_config() argument
212 denali_phy = chan->publ->denali_phy; in phy_io_config()
213 denali_ctl = chan->pctl->denali_ctl; in phy_io_config()
535 static void set_ds_odt(const struct chan_info *chan, in set_ds_odt() argument
552 denali_phy = chan->publ->denali_phy; in set_ds_odt()
553 denali_ctl = chan->pctl->denali_ctl; in set_ds_odt()
[all …]
H A Dsdram_rk3188.c37 struct chan_info chan[1]; member
258 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() argument
261 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg()
262 struct rk3188_msch *msch = chan->msch; in phy_cfg()
379 static void set_bandwidth_ratio(const struct chan_info *chan, int channel, in set_bandwidth_ratio() argument
382 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio()
383 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio()
384 struct rk3188_msch *msch = chan->msch; in set_bandwidth_ratio()
417 static int data_training(const struct chan_info *chan, int channel, in data_training() argument
425 struct rk3288_ddr_publ *publ = chan->publ; in data_training()
[all …]
H A Dsdram_rk3288.c39 struct chan_info chan[2]; member
292 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() argument
295 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg()
296 struct rk3288_msch *msch = chan->msch; in phy_cfg()
437 static void set_bandwidth_ratio(const struct chan_info *chan, int channel, in set_bandwidth_ratio() argument
440 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio()
441 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio()
442 struct rk3288_msch *msch = chan->msch; in set_bandwidth_ratio()
475 static int data_training(const struct chan_info *chan, int channel, in data_training() argument
483 struct rk3288_ddr_publ *publ = chan->publ; in data_training()
[all …]
H A Dsdram_rk322x.c33 struct chan_info chan[1]; member
162 static void memory_init(struct chan_info *chan, in memory_init() argument
165 struct rk322x_ddr_pctl *pctl = chan->pctl; in memory_init()
230 static u32 data_training(struct chan_info *chan) in data_training() argument
232 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training()
233 struct rk322x_ddr_pctl *pctl = chan->pctl; in data_training()
365 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in phy_softreset()
380 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; in set_bw()
381 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in set_bw()
468 static void phy_cfg(struct chan_info *chan, in phy_cfg() argument
[all …]
H A Ddmc-rk3368.c42 struct rk3288_sdram_channel chan; member
620 (1 << (col + params->chan.bw - 1)); in sdram_col_row_detect()
653 params->chan.col = col; in sdram_col_row_detect()
654 params->chan.cs0_row = row; in sdram_col_row_detect()
655 params->chan.cs1_row = row; in sdram_col_row_detect()
656 params->chan.row_3_4 = 0; in sdram_col_row_detect()
665 const u8 cols = params->chan.col - ((params->chan.bw == 2) ? 0 : 1); in msch_biu_config()
666 const u8 rows = params->chan.cs0_row; in msch_biu_config()
776 const struct rk3288_sdram_channel *info = &params->chan; in dram_all_config()
778 const int chan = 0; in dram_all_config() local
[all …]
/rk3399_rockchip-uboot/include/
H A Dmailbox-uclass.h38 int (*of_xlate)(struct mbox_chan *chan,
51 int (*request)(struct mbox_chan *chan);
60 int (*free)(struct mbox_chan *chan);
68 int (*send)(struct mbox_chan *chan, const void *data);
80 int (*recv)(struct mbox_chan *chan, void *data);
H A Dmailbox.h83 int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
102 struct mbox_chan *chan);
111 int mbox_free(struct mbox_chan *chan);
127 int mbox_send(struct mbox_chan *chan, const void *data);
147 int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/
H A Dsdram_rk3066.c37 struct chan_info chan[1]; member
247 static void phy_cfg(const struct chan_info *chan, int channel, in phy_cfg() argument
250 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg()
251 struct rk3188_msch *msch = chan->msch; in phy_cfg()
368 static void set_bandwidth_ratio(const struct chan_info *chan, int channel, in set_bandwidth_ratio() argument
371 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio()
372 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio()
373 struct rk3188_msch *msch = chan->msch; in set_bandwidth_ratio()
404 static int data_training(const struct chan_info *chan, int channel, in data_training() argument
412 struct rk3288_ddr_publ *publ = chan->publ; in data_training()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap3/
H A Ddma.h12 int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst,
14 int omap3_dma_start_transfer(uint32_t chan);
15 int omap3_dma_wait_for_transfer(uint32_t chan);
16 int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config);
17 int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config);
/rk3399_rockchip-uboot/drivers/dma/
H A Dapbh_dma.c500 static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan) in mxs_dma_wait_complete() argument
506 ret = mxs_dma_validate_chan(chan); in mxs_dma_wait_complete()
511 1 << chan, timeout)) { in mxs_dma_wait_complete()
513 mxs_dma_reset(chan); in mxs_dma_wait_complete()
522 int mxs_dma_go(int chan) in mxs_dma_go() argument
529 mxs_dma_enable_irq(chan, 1); in mxs_dma_go()
530 mxs_dma_enable(chan); in mxs_dma_go()
533 ret = mxs_dma_wait_complete(timeout, chan); in mxs_dma_go()
536 mxs_dma_finish(chan, &tmp_desc_list); in mxs_dma_go()
539 mxs_dma_ack_irq(chan); in mxs_dma_go()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-bcm283x/
H A Dmbox.c14 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv) in bcm2835_mbox_call_raw() argument
55 val = BCM2835_MBOX_PACK(chan, send); in bcm2835_mbox_call_raw()
78 if (BCM2835_MBOX_UNPACK_CHAN(val) != chan) { in bcm2835_mbox_call_raw()
102 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer) in bcm2835_mbox_call_prop() argument
118 ret = bcm2835_mbox_call_raw(chan, in bcm2835_mbox_call_prop()
/rk3399_rockchip-uboot/arch/arm/include/asm/mach-imx/
H A Ddma.h154 int mxs_dma_go(int chan);
156 int mxs_dma_init_channel(int chan);
157 int mxs_dma_release(int chan);
159 void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc);

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