500 static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)  in mxs_dma_wait_complete()  argument
506 	ret = mxs_dma_validate_chan(chan);  in mxs_dma_wait_complete()
511 				1 << chan, timeout)) {  in mxs_dma_wait_complete()
513 		mxs_dma_reset(chan);  in mxs_dma_wait_complete()
522 int mxs_dma_go(int chan)  in mxs_dma_go()  argument
529 	mxs_dma_enable_irq(chan, 1);  in mxs_dma_go()
530 	mxs_dma_enable(chan);  in mxs_dma_go()
533 	ret = mxs_dma_wait_complete(timeout, chan);  in mxs_dma_go()
536 	mxs_dma_finish(chan, &tmp_desc_list);  in mxs_dma_go()
539 	mxs_dma_ack_irq(chan);  in mxs_dma_go()
540 	mxs_dma_reset(chan);  in mxs_dma_go()
541 	mxs_dma_enable_irq(chan, 0);  in mxs_dma_go()
542 	mxs_dma_disable(chan);  in mxs_dma_go()
553 void mxs_dma_circ_start(int chan, struct mxs_dma_desc *pdesc)  in mxs_dma_circ_start()  argument
560 	mxs_dma_enable_irq(chan, 1);  in mxs_dma_circ_start()
563 		&apbh_regs->ch[chan].hw_apbh_ch_nxtcmdar);  in mxs_dma_circ_start()
564 	writel(1, &apbh_regs->ch[chan].hw_apbh_ch_sema);  in mxs_dma_circ_start()
565 	writel(1 << (chan + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),  in mxs_dma_circ_start()