1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _XOR_H 8*f1df9364SStefan Roese #define _XOR_H 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese #define SRAM_BASE 0x40000000 11*f1df9364SStefan Roese 12*f1df9364SStefan Roese #include "ddr3_hws_hw_training_def.h" 13*f1df9364SStefan Roese 14*f1df9364SStefan Roese #define MV_XOR_MAX_UNIT 2 /* XOR unit == XOR engine */ 15*f1df9364SStefan Roese #define MV_XOR_MAX_CHAN 4 /* total channels for all units */ 16*f1df9364SStefan Roese #define MV_XOR_MAX_CHAN_PER_UNIT 2 /* channels for units */ 17*f1df9364SStefan Roese 18*f1df9364SStefan Roese #define MV_IS_POWER_OF_2(num) (((num) != 0) && (((num) & ((num) - 1)) == 0)) 19*f1df9364SStefan Roese 20*f1df9364SStefan Roese /* 21*f1df9364SStefan Roese * This structure describes address space window. Window base can be 22*f1df9364SStefan Roese * 64 bit, window size up to 4GB 23*f1df9364SStefan Roese */ 24*f1df9364SStefan Roese struct addr_win { 25*f1df9364SStefan Roese u32 base_low; /* 32bit base low */ 26*f1df9364SStefan Roese u32 base_high; /* 32bit base high */ 27*f1df9364SStefan Roese u32 size; /* 32bit size */ 28*f1df9364SStefan Roese }; 29*f1df9364SStefan Roese 30*f1df9364SStefan Roese /* This structure describes SoC units address decode window */ 31*f1df9364SStefan Roese struct unit_win_info { 32*f1df9364SStefan Roese struct addr_win addr_win; /* An address window */ 33*f1df9364SStefan Roese int enable; /* Address decode window is enabled/disabled */ 34*f1df9364SStefan Roese u8 attrib; /* chip select attributes */ 35*f1df9364SStefan Roese u8 target_id; /* Target Id of this MV_TARGET */ 36*f1df9364SStefan Roese }; 37*f1df9364SStefan Roese 38*f1df9364SStefan Roese /* 39*f1df9364SStefan Roese * This enumerator describes the type of functionality the XOR channel 40*f1df9364SStefan Roese * can have while using the same data structures. 41*f1df9364SStefan Roese */ 42*f1df9364SStefan Roese enum xor_type { 43*f1df9364SStefan Roese MV_XOR, /* XOR channel functions as XOR accelerator */ 44*f1df9364SStefan Roese MV_DMA, /* XOR channel functions as IDMA channel */ 45*f1df9364SStefan Roese MV_CRC32 /* XOR channel functions as CRC 32 calculator */ 46*f1df9364SStefan Roese }; 47*f1df9364SStefan Roese 48*f1df9364SStefan Roese enum mv_state { 49*f1df9364SStefan Roese MV_IDLE, 50*f1df9364SStefan Roese MV_ACTIVE, 51*f1df9364SStefan Roese MV_PAUSED, 52*f1df9364SStefan Roese MV_UNDEFINED_STATE 53*f1df9364SStefan Roese }; 54*f1df9364SStefan Roese 55*f1df9364SStefan Roese /* 56*f1df9364SStefan Roese * This enumerator describes the set of commands that can be applied on 57*f1df9364SStefan Roese * an engine (e.g. IDMA, XOR). Appling a comman depends on the current 58*f1df9364SStefan Roese * status (see MV_STATE enumerator) 59*f1df9364SStefan Roese * 60*f1df9364SStefan Roese * Start can be applied only when status is IDLE 61*f1df9364SStefan Roese * Stop can be applied only when status is IDLE, ACTIVE or PAUSED 62*f1df9364SStefan Roese * Pause can be applied only when status is ACTIVE 63*f1df9364SStefan Roese * Restart can be applied only when status is PAUSED 64*f1df9364SStefan Roese */ 65*f1df9364SStefan Roese enum mv_command { 66*f1df9364SStefan Roese MV_START, /* Start */ 67*f1df9364SStefan Roese MV_STOP, /* Stop */ 68*f1df9364SStefan Roese MV_PAUSE, /* Pause */ 69*f1df9364SStefan Roese MV_RESTART /* Restart */ 70*f1df9364SStefan Roese }; 71*f1df9364SStefan Roese 72*f1df9364SStefan Roese enum xor_override_target { 73*f1df9364SStefan Roese SRC_ADDR0, /* Source Address #0 Control */ 74*f1df9364SStefan Roese SRC_ADDR1, /* Source Address #1 Control */ 75*f1df9364SStefan Roese SRC_ADDR2, /* Source Address #2 Control */ 76*f1df9364SStefan Roese SRC_ADDR3, /* Source Address #3 Control */ 77*f1df9364SStefan Roese SRC_ADDR4, /* Source Address #4 Control */ 78*f1df9364SStefan Roese SRC_ADDR5, /* Source Address #5 Control */ 79*f1df9364SStefan Roese SRC_ADDR6, /* Source Address #6 Control */ 80*f1df9364SStefan Roese SRC_ADDR7, /* Source Address #7 Control */ 81*f1df9364SStefan Roese XOR_DST_ADDR, /* Destination Address Control */ 82*f1df9364SStefan Roese XOR_NEXT_DESC /* Next Descriptor Address Control */ 83*f1df9364SStefan Roese }; 84*f1df9364SStefan Roese 85*f1df9364SStefan Roese enum mv_state mv_xor_state_get(u32 chan); 86*f1df9364SStefan Roese void mv_xor_hal_init(u32 xor_chan_num); 87*f1df9364SStefan Roese int mv_xor_ctrl_set(u32 chan, u32 xor_ctrl); 88*f1df9364SStefan Roese int mv_xor_command_set(u32 chan, enum mv_command command); 89*f1df9364SStefan Roese int mv_xor_override_set(u32 chan, enum xor_override_target target, u32 win_num, 90*f1df9364SStefan Roese int enable); 91*f1df9364SStefan Roese 92*f1df9364SStefan Roese #endif 93