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Searched refs:cfg (Results 1 – 25 of 421) sorted by relevance

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/rk3399_rockchip-uboot/drivers/video/
H A Dssd2828.c154 static u32 read_hw_register(const struct ssd2828_config *cfg, u8 regnum) in read_hw_register() argument
156 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); in read_hw_register()
157 return soft_spi_xfer_24bit_3wire(cfg, 0x730000); in read_hw_register()
163 static void write_hw_register(const struct ssd2828_config *cfg, u8 regnum, in write_hw_register() argument
166 soft_spi_xfer_24bit_3wire(cfg, 0x700000 | regnum); in write_hw_register()
167 soft_spi_xfer_24bit_3wire(cfg, 0x720000 | val); in write_hw_register()
173 static void send_mipi_dcs_command(const struct ssd2828_config *cfg, u8 cmdnum) in send_mipi_dcs_command() argument
176 write_hw_register(cfg, SSD2828_PSCR1, 1); in send_mipi_dcs_command()
178 write_hw_register(cfg, SSD2828_PDR, cmdnum); in send_mipi_dcs_command()
184 static void ssd2828_reset(const struct ssd2828_config *cfg) in ssd2828_reset() argument
[all …]
/rk3399_rockchip-uboot/include/linux/
H A Dkconfig.h20 #define config_enabled(cfg) _config_enabled(cfg) argument
59 #define config_val(cfg) _config_val(_IS_TPL, cfg) argument
60 #define _config_val(x, cfg) __config_val(x, cfg) argument
61 #define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) argument
62 #define ___config_val(arg1_or_junk, cfg) \ argument
63 ____config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg)
66 #define config_val(cfg) _config_val(_IS_SPL, cfg) argument
67 #define _config_val(x, cfg) __config_val(x, cfg) argument
68 #define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg) argument
69 #define ___config_val(arg1_or_junk, cfg) \ argument
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/rk3399_rockchip-uboot/drivers/video/exynos/
H A Dexynos_fb.c106 unsigned int cfg = 0; in exynos_fimd_set_dualrgb() local
109 cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT | in exynos_fimd_set_dualrgb()
113 cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) | in exynos_fimd_set_dualrgb()
117 writel(cfg, &reg->dualrgb); in exynos_fimd_set_dualrgb()
124 unsigned int cfg = 0; in exynos_fimd_set_dp_clkcon() local
127 cfg = EXYNOS_DP_CLK_ENABLE; in exynos_fimd_set_dp_clkcon()
129 writel(cfg, &reg->dp_mie_clkcon); in exynos_fimd_set_dp_clkcon()
136 unsigned int cfg = 0; in exynos_fimd_set_par() local
139 cfg = readl((unsigned int)&reg->wincon0 + in exynos_fimd_set_par()
142 cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE | in exynos_fimd_set_par()
[all …]
/rk3399_rockchip-uboot/drivers/ddr/altera/
H A Dsdram.c43 static int get_errata_rows(const struct socfpga_sdram_config *cfg) in get_errata_rows() argument
49 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> in get_errata_rows()
52 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >> in get_errata_rows()
55 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >> in get_errata_rows()
58 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >> in get_errata_rows()
269 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg) in sdr_get_ctrlcfg() argument
272 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >> in sdr_get_ctrlcfg()
275 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >> in sdr_get_ctrlcfg()
278 u32 ctrl_cfg = cfg->ctrl_cfg; in sdr_get_ctrlcfg()
307 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg) in sdr_get_addr_rw() argument
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/rk3399_rockchip-uboot/include/fsl-mc/
H A Dfsl_dpni.h56 #define DPNI_PREP_EXTENDED_CFG(ext, cfg) \ argument
58 MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \
59 MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \
60 MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \
61 MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \
62 MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \
63 MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \
64 MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \
65 MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \
66 MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \
[all …]
H A Dfsl_dpmac.h33 #define DPMAC_CMD_CREATE(cmd, cfg) \ argument
34 MC_CMD_OP(cmd, 0, 0, 32, int, cfg->mac_id)
53 #define DPMAC_CMD_MDIO_READ(cmd, cfg) \ argument
55 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
56 MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
64 #define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ argument
66 MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \
67 MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \
68 MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \
72 #define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ argument
[all …]
/rk3399_rockchip-uboot/drivers/phy/
H A Dphy-rockchip-naneng-combphy.c88 const struct rockchip_combphy_cfg *cfg; member
105 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready() local
108 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
109 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
111 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
112 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
122 if (priv->cfg->combphy_cfg) { in rockchip_combphy_pcie_init()
123 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_pcie_init()
130 if (priv->cfg->force_det_out) { in rockchip_combphy_pcie_init()
141 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_usb3_init() local
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/rk3399_rockchip-uboot/drivers/power/
H A Daxp818.c33 u8 cfg = axp818_mvolt_to_cfg(mvolt, 1600, 3400, 100); in axp_set_dcdc1() local
39 ret = pmic_bus_write(AXP818_DCDC1_CTRL, cfg); in axp_set_dcdc1()
50 u8 cfg; in axp_set_dcdc2() local
53 cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20); in axp_set_dcdc2()
55 cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10); in axp_set_dcdc2()
61 ret = pmic_bus_write(AXP818_DCDC2_CTRL, cfg); in axp_set_dcdc2()
72 u8 cfg; in axp_set_dcdc3() local
75 cfg = 70 + axp818_mvolt_to_cfg(mvolt, 1220, 1300, 20); in axp_set_dcdc3()
77 cfg = axp818_mvolt_to_cfg(mvolt, 500, 1200, 10); in axp_set_dcdc3()
83 ret = pmic_bus_write(AXP818_DCDC3_CTRL, cfg); in axp_set_dcdc3()
[all …]
H A Daxp209.c26 u8 cfg, current; in axp_set_dcdc2() local
36 cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25); in axp_set_dcdc2()
40 current != cfg) { in axp_set_dcdc2()
41 if (current < cfg) in axp_set_dcdc2()
56 u8 cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25); in axp_set_dcdc3() local
63 rc = pmic_bus_write(AXP209_DCDC3_VOLTAGE, cfg); in axp_set_dcdc3()
73 u8 cfg, reg; in axp_set_aldo2() local
79 cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100); in axp_set_aldo2()
86 reg = (reg & 0x0f) | (cfg << 4); in axp_set_aldo2()
96 u8 cfg; in axp_set_aldo3() local
[all …]
H A Daxp809.c33 u8 cfg = axp809_mvolt_to_cfg(mvolt, 1600, 3400, 100); in axp_set_dcdc1() local
39 ret = pmic_bus_write(AXP809_DCDC1_CTRL, cfg); in axp_set_dcdc1()
55 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20); in axp_set_dcdc2() local
61 ret = pmic_bus_write(AXP809_DCDC2_CTRL, cfg); in axp_set_dcdc2()
72 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1860, 20); in axp_set_dcdc3() local
78 ret = pmic_bus_write(AXP809_DCDC3_CTRL, cfg); in axp_set_dcdc3()
89 u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20); in axp_set_dcdc4() local
92 cfg = 0x30 + axp809_mvolt_to_cfg(mvolt, 1800, 2600, 100); in axp_set_dcdc4()
98 ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg); in axp_set_dcdc4()
109 u8 cfg = axp809_mvolt_to_cfg(mvolt, 1000, 2550, 50); in axp_set_dcdc5() local
[all …]
H A Daxp221.c32 u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100); in axp_set_dcdc1() local
38 ret = pmic_bus_write(AXP221_DCDC1_CTRL, cfg); in axp_set_dcdc1()
54 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); in axp_set_dcdc2() local
60 ret = pmic_bus_write(AXP221_DCDC2_CTRL, cfg); in axp_set_dcdc2()
71 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20); in axp_set_dcdc3() local
77 ret = pmic_bus_write(AXP221_DCDC3_CTRL, cfg); in axp_set_dcdc3()
88 u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20); in axp_set_dcdc4() local
94 ret = pmic_bus_write(AXP221_DCDC4_CTRL, cfg); in axp_set_dcdc4()
105 u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50); in axp_set_dcdc5() local
111 ret = pmic_bus_write(AXP221_DCDC5_CTRL, cfg); in axp_set_dcdc5()
[all …]
/rk3399_rockchip-uboot/board/gateworks/gw_ventana/
H A Deeprom.c125 struct ventana_eeprom_config *cfg = econfig; in get_config() local
127 while (cfg->name) { in get_config()
128 if (0 == strcmp(name, cfg->name)) in get_config()
129 return cfg; in get_config()
130 cfg++; in get_config()
140 struct ventana_eeprom_config *cfg; in do_econfig() local
155 cfg = econfig; in do_econfig()
156 while (cfg->name) { in do_econfig()
157 printf("%s: %d\n", cfg->name, in do_econfig()
158 test_bit(cfg->bit, econfig_bytes) ? 1 : 0); in do_econfig()
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/rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/
H A Dfsl_ls1_serdes.c44 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane() local
50 cfg &= RCWSR4_SRDS1_PRTCL_MASK; in serdes_get_first_lane()
51 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; in serdes_get_first_lane()
56 cfg &= RCWSR4_SRDS2_PRTCL_MASK; in serdes_get_first_lane()
57 cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT; in serdes_get_first_lane()
65 if (unlikely(cfg == 0)) in serdes_get_first_lane()
69 if (serdes_get_prtcl(sd, cfg, i) == device) in serdes_get_first_lane()
80 u32 cfg; in serdes_init() local
83 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()
84 cfg >>= sd_prctl_shift; in serdes_init()
[all …]
/rk3399_rockchip-uboot/drivers/adc/
H A Dexynos-adc.c41 unsigned int cfg; in exynos_adc_start_channel() local
44 cfg = readl(&regs->con2); in exynos_adc_start_channel()
45 cfg &= ~ADC_V2_CON2_CHAN_SEL_MASK; in exynos_adc_start_channel()
46 cfg |= ADC_V2_CON2_CHAN_SEL(channel); in exynos_adc_start_channel()
47 writel(cfg, &regs->con2); in exynos_adc_start_channel()
50 cfg = readl(&regs->con1); in exynos_adc_start_channel()
51 writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1); in exynos_adc_start_channel()
62 unsigned int cfg; in exynos_adc_stop() local
65 cfg = readl(&regs->con1); in exynos_adc_stop()
66 cfg |= ~ADC_V2_CON1_STC_EN; in exynos_adc_stop()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch3_serdes.c54 u32 cfg = 0; in serdes_get_first_lane() local
60 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); in serdes_get_first_lane()
61 cfg &= FSL_CHASSIS3_SRDS1_PRTCL_MASK; in serdes_get_first_lane()
62 cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; in serdes_get_first_lane()
67 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); in serdes_get_first_lane()
68 cfg &= FSL_CHASSIS3_SRDS2_PRTCL_MASK; in serdes_get_first_lane()
69 cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT; in serdes_get_first_lane()
77 if (cfg == 0) in serdes_get_first_lane()
81 if (serdes_get_prtcl(sd, cfg, i) == device) in serdes_get_first_lane()
92 u32 cfg; in serdes_init() local
[all …]
/rk3399_rockchip-uboot/drivers/memory/
H A Dti-aemif.c38 static void aemif_configure(int cs, struct aemif_config *cfg) in aemif_configure() argument
42 if (cfg->mode == AEMIF_MODE_NAND) { in aemif_configure()
47 } else if (cfg->mode == AEMIF_MODE_ONENAND) { in aemif_configure()
55 set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); in aemif_configure()
56 set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); in aemif_configure()
57 set_config_field(tmp, WR_SETUP, cfg->wr_setup); in aemif_configure()
58 set_config_field(tmp, WR_STROBE, cfg->wr_strobe); in aemif_configure()
59 set_config_field(tmp, WR_HOLD, cfg->wr_hold); in aemif_configure()
60 set_config_field(tmp, RD_SETUP, cfg->rd_setup); in aemif_configure()
61 set_config_field(tmp, RD_STROBE, cfg->rd_strobe); in aemif_configure()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dsystem.c37 unsigned int cfg = 0; in exynos4_set_system_display() local
44 cfg = readl(&sysreg->display_ctrl); in exynos4_set_system_display()
45 cfg |= (1 << 1); in exynos4_set_system_display()
46 writel(cfg, &sysreg->display_ctrl); in exynos4_set_system_display()
53 unsigned int cfg = 0; in exynos5_set_system_display() local
60 cfg = readl(&sysreg->disp1blk_cfg); in exynos5_set_system_display()
61 cfg |= (1 << 15); in exynos5_set_system_display()
62 writel(cfg, &sysreg->disp1blk_cfg); in exynos5_set_system_display()
/rk3399_rockchip-uboot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c71 int cm_basic_init(const struct cm_config * const cfg) in cm_basic_init() argument
138 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); in cm_basic_init()
139 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); in cm_basic_init()
140 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); in cm_basic_init()
149 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()
152 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); in cm_basic_init()
155 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); in cm_basic_init()
158 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); in cm_basic_init()
161 writel(cfg->cfg2fuser0clk, in cm_basic_init()
165 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); in cm_basic_init()
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/
H A Drockchip-inno-hdmi-phy.c202 const struct post_pll_config *cfg,
206 const struct pre_pll_config *cfg);
457 const struct post_pll_config *cfg = post_pll_cfg_table; in inno_hdmi_phy_power_on() local
483 for (; cfg->tmdsclock != ~0UL; cfg++) in inno_hdmi_phy_power_on()
484 if (tmdsclock <= cfg->tmdsclock && in inno_hdmi_phy_power_on()
485 cfg->version & chipversion) in inno_hdmi_phy_power_on()
492 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL) in inno_hdmi_phy_power_on()
497 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg); in inno_hdmi_phy_power_on()
543 const struct pre_pll_config *cfg = pre_pll_cfg_table; in inno_hdmi_phy_clk_set_rate() local
546 for (; cfg->pixclock != ~0UL; cfg++) in inno_hdmi_phy_clk_set_rate()
[all …]
/rk3399_rockchip-uboot/drivers/dma/
H A Dti-edma3.c51 void qedma3_start(u32 base, struct edma3_channel_config *cfg) in qedma3_start() argument
56 if (cfg->complete_code < 32) in qedma3_start()
57 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICR); in qedma3_start()
59 __raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH); in qedma3_start()
62 qchmap = ((EDMA3_CHMAP_PARSET_MASK & cfg->slot) in qedma3_start()
64 (cfg->trigger_slot_word << EDMA3_CHMAP_TRIGWORD_SHIFT); in qedma3_start()
66 __raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum)); in qedma3_start()
69 __raw_writel(1 << cfg->chnum, base + EDMA3_QSECR); in qedma3_start()
70 __raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR); in qedma3_start()
73 __raw_writel(1 << cfg->chnum, base + EDMA3_QEESR); in qedma3_start()
[all …]
/rk3399_rockchip-uboot/cmd/
H A Dpxe.c1072 struct pxe_menu *cfg, int nest_level);
1083 struct pxe_menu *cfg, int nest_level) in handle_include() argument
1107 ret = parse_pxefile_top(cmdtp, buf, base, cfg, nest_level); in handle_include()
1123 static int parse_menu(cmd_tbl_t *cmdtp, char **c, struct pxe_menu *cfg, in parse_menu() argument
1134 err = parse_sliteral(c, &cfg->title); in parse_menu()
1139 err = handle_include(cmdtp, c, base, cfg, in parse_menu()
1159 static int parse_label_menu(char **c, struct pxe_menu *cfg, in parse_label_menu() argument
1171 if (!cfg->default_label) in parse_label_menu()
1172 cfg->default_label = strdup(label->name); in parse_label_menu()
1174 if (!cfg->default_label) in parse_label_menu()
[all …]
/rk3399_rockchip-uboot/drivers/mmc/
H A Dsandbox_mmc.c18 struct mmc_config cfg; member
114 struct mmc_config *cfg = &plat->cfg; in sandbox_mmc_bind() local
116 cfg->name = dev->name; in sandbox_mmc_bind()
117 cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT; in sandbox_mmc_bind()
118 cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; in sandbox_mmc_bind()
119 cfg->f_min = 1000000; in sandbox_mmc_bind()
120 cfg->f_max = 52000000; in sandbox_mmc_bind()
121 cfg->b_max = U32_MAX; in sandbox_mmc_bind()
123 return mmc_bind(dev, &plat->mmc, cfg); in sandbox_mmc_bind()
H A Dmmc_legacy.c96 printf("%s: %d", m->cfg->name, m->block_dev.devnum); in print_mmc_devices()
129 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) in mmc_create() argument
133 mmc->cfg = cfg; in mmc_create()
143 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) in mmc_create() argument
149 if (cfg == NULL || cfg->f_min == 0 || in mmc_create()
150 cfg->f_max == 0 || cfg->b_max == 0) in mmc_create()
154 if (cfg->ops == NULL || cfg->ops->send_cmd == NULL) in mmc_create()
162 mmc->cfg = cfg; in mmc_create()
180 bdesc->part_type = mmc->cfg->part_type; in mmc_create()
/rk3399_rockchip-uboot/include/dt-bindings/dma/
H A Dat91.h35 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ argument
42 #define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ argument
49 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ argument
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet2_serdes.c125 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane() local
131 cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in serdes_get_first_lane()
132 cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; in serdes_get_first_lane()
137 cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL; in serdes_get_first_lane()
138 cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; in serdes_get_first_lane()
143 cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; in serdes_get_first_lane()
144 cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; in serdes_get_first_lane()
149 cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; in serdes_get_first_lane()
150 cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; in serdes_get_first_lane()
158 if (unlikely(cfg == 0)) in serdes_get_first_lane()
[all …]

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