202 			const struct post_pll_config *cfg,
206 			      const struct pre_pll_config *cfg);
457 	const struct post_pll_config *cfg = post_pll_cfg_table;  in inno_hdmi_phy_power_on()  local
483 	for (; cfg->tmdsclock != ~0UL; cfg++)  in inno_hdmi_phy_power_on()
484 		if (tmdsclock <= cfg->tmdsclock &&  in inno_hdmi_phy_power_on()
485 		    cfg->version & chipversion)  in inno_hdmi_phy_power_on()
492 	if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL)  in inno_hdmi_phy_power_on()
497 		return inno->plat_data->ops->power_on(inno, cfg, phy_cfg);  in inno_hdmi_phy_power_on()
543 	const struct pre_pll_config *cfg = pre_pll_cfg_table;  in inno_hdmi_phy_clk_set_rate()  local
546 	for (; cfg->pixclock != ~0UL; cfg++)  in inno_hdmi_phy_clk_set_rate()
547 		if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)  in inno_hdmi_phy_clk_set_rate()
550 	if (cfg->pixclock == ~0UL) {  in inno_hdmi_phy_clk_set_rate()
556 		inno->plat_data->ops->pre_pll_update(inno, cfg);  in inno_hdmi_phy_clk_set_rate()
583 			      const struct post_pll_config *cfg,  in inno_hdmi_phy_rk3228_power_on()  argument
598 	v = POST_PLL_PRE_DIV(cfg->prediv);  in inno_hdmi_phy_rk3228_power_on()
602 	v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8);  in inno_hdmi_phy_rk3228_power_on()
604 	inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_power_on()
606 	if (cfg->postdiv == 1) {  in inno_hdmi_phy_rk3228_power_on()
618 		v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1);  in inno_hdmi_phy_rk3228_power_on()
647 	if (cfg->tmdsclock > 340000000)  in inno_hdmi_phy_rk3228_power_on()
669 				    const struct pre_pll_config *cfg)  in inno_hdmi_phy_rk3228_pre_pll_update()  argument
678 	v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) |  in inno_hdmi_phy_rk3228_pre_pll_update()
679 	    PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv);  in inno_hdmi_phy_rk3228_pre_pll_update()
682 	inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv));  in inno_hdmi_phy_rk3228_pre_pll_update()
685 	v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) |  in inno_hdmi_phy_rk3228_pre_pll_update()
686 	    PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a);  in inno_hdmi_phy_rk3228_pre_pll_update()
690 	v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |  in inno_hdmi_phy_rk3228_pre_pll_update()
691 	    PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d);  in inno_hdmi_phy_rk3228_pre_pll_update()
696 	v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |  in inno_hdmi_phy_rk3228_pre_pll_update()
697 	    PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |  in inno_hdmi_phy_rk3228_pre_pll_update()
698 	    PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b);  in inno_hdmi_phy_rk3228_pre_pll_update()
731 			      const struct post_pll_config *cfg,  in inno_hdmi_phy_rk3328_power_on()  argument
741 	val = cfg->fbdiv & 0xff;  in inno_hdmi_phy_rk3328_power_on()
743 	if (cfg->postdiv == 1) {  in inno_hdmi_phy_rk3328_power_on()
745 		val = (cfg->fbdiv >> 8) | cfg->prediv;  in inno_hdmi_phy_rk3328_power_on()
748 		val = (cfg->postdiv / 2) - 1;  in inno_hdmi_phy_rk3328_power_on()
750 		val = (cfg->fbdiv >> 8) | cfg->prediv;  in inno_hdmi_phy_rk3328_power_on()
831 				    const struct pre_pll_config *cfg)  in inno_hdmi_phy_rk3328_pre_pll_update()  argument
838 	inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);  in inno_hdmi_phy_rk3328_pre_pll_update()
839 	inno_write(inno, 0xa1, cfg->prediv);  in inno_hdmi_phy_rk3328_pre_pll_update()
840 	if (cfg->fracdiv)  in inno_hdmi_phy_rk3328_pre_pll_update()
841 		val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0;  in inno_hdmi_phy_rk3328_pre_pll_update()
843 		val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0;  in inno_hdmi_phy_rk3328_pre_pll_update()
845 	inno_write(inno, 0xa3, cfg->fbdiv & 0xff);  in inno_hdmi_phy_rk3328_pre_pll_update()
846 	val = (cfg->pclk_div_a & 0x1f) |  in inno_hdmi_phy_rk3328_pre_pll_update()
847 	      ((cfg->pclk_div_b & 3) << 5);  in inno_hdmi_phy_rk3328_pre_pll_update()
849 	val = (cfg->pclk_div_d & 0x1f) |  in inno_hdmi_phy_rk3328_pre_pll_update()
850 	      ((cfg->pclk_div_c & 3) << 5);  in inno_hdmi_phy_rk3328_pre_pll_update()
852 	val = ((cfg->tmds_div_a & 3) << 4) |  in inno_hdmi_phy_rk3328_pre_pll_update()
853 	      ((cfg->tmds_div_b & 3) << 2) |  in inno_hdmi_phy_rk3328_pre_pll_update()
854 	      (cfg->tmds_div_c & 3);  in inno_hdmi_phy_rk3328_pre_pll_update()
857 	if (cfg->fracdiv) {  in inno_hdmi_phy_rk3328_pre_pll_update()
858 		val = cfg->fracdiv & 0xff;  in inno_hdmi_phy_rk3328_pre_pll_update()
860 		val = (cfg->fracdiv >> 8) & 0xff;  in inno_hdmi_phy_rk3328_pre_pll_update()
862 		val = (cfg->fracdiv >> 16) & 0xff;  in inno_hdmi_phy_rk3328_pre_pll_update()
924 			      const struct post_pll_config *cfg,  in inno_hdmi_phy_rk3528_power_on()  argument
934 	val = cfg->prediv;  in inno_hdmi_phy_rk3528_power_on()
937 	if (cfg->postdiv == 1) {  in inno_hdmi_phy_rk3528_power_on()
941 		val = (cfg->postdiv / 2) - 1;  in inno_hdmi_phy_rk3528_power_on()
946 	val = cfg->fbdiv & 0xff;  in inno_hdmi_phy_rk3528_power_on()
948 	val = (cfg->fbdiv >> 8) & BIT(0);  in inno_hdmi_phy_rk3528_power_on()
1041 				    const struct pre_pll_config *cfg)  in inno_hdmi_phy_rk3528_pre_pll_update()  argument
1051 	inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);  in inno_hdmi_phy_rk3528_pre_pll_update()
1052 	inno_write(inno, 0xa1, cfg->prediv);  in inno_hdmi_phy_rk3528_pre_pll_update()
1053 	if (cfg->fracdiv)  in inno_hdmi_phy_rk3528_pre_pll_update()
1054 		val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0;  in inno_hdmi_phy_rk3528_pre_pll_update()
1056 		val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0;  in inno_hdmi_phy_rk3528_pre_pll_update()
1058 	inno_write(inno, 0xa3, cfg->fbdiv & 0xff);  in inno_hdmi_phy_rk3528_pre_pll_update()
1059 	val = (cfg->pclk_div_a & 0x1f) |  in inno_hdmi_phy_rk3528_pre_pll_update()
1060 	      ((cfg->pclk_div_b & 3) << 5);  in inno_hdmi_phy_rk3528_pre_pll_update()
1062 	val = (cfg->pclk_div_d & 0x1f) |  in inno_hdmi_phy_rk3528_pre_pll_update()
1063 	      ((cfg->pclk_div_c & 3) << 5);  in inno_hdmi_phy_rk3528_pre_pll_update()
1065 	val = ((cfg->tmds_div_a & 3) << 4) |  in inno_hdmi_phy_rk3528_pre_pll_update()
1066 	      ((cfg->tmds_div_b & 3) << 2) |  in inno_hdmi_phy_rk3528_pre_pll_update()
1067 	      (cfg->tmds_div_c & 3);  in inno_hdmi_phy_rk3528_pre_pll_update()
1070 	if (cfg->fracdiv) {  in inno_hdmi_phy_rk3528_pre_pll_update()
1071 		val = cfg->fracdiv & 0xff;  in inno_hdmi_phy_rk3528_pre_pll_update()
1073 		val = (cfg->fracdiv >> 8) & 0xff;  in inno_hdmi_phy_rk3528_pre_pll_update()
1075 		val = (cfg->fracdiv >> 16) & 0xff;  in inno_hdmi_phy_rk3528_pre_pll_update()
1351 	const struct pre_pll_config *cfg = pre_pll_cfg_table;  in inno_hdmi_phy_clk_round_rate()  local
1354 	for (; cfg->pixclock != ~0UL; cfg++)  in inno_hdmi_phy_clk_round_rate()
1355 		if (cfg->pixclock == rate)  in inno_hdmi_phy_clk_round_rate()
1363 	     cfg->fracdiv) || cfg->pixclock > 600000000)  in inno_hdmi_phy_clk_round_rate()
1372 		return cfg->pixclock;  in inno_hdmi_phy_clk_round_rate()
1383 	return cfg->pixclock;  in inno_hdmi_phy_clk_round_rate()