51 void qedma3_start(u32 base, struct edma3_channel_config *cfg)  in qedma3_start()  argument
56 	if (cfg->complete_code < 32)  in qedma3_start()
57 		__raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);  in qedma3_start()
59 		__raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);  in qedma3_start()
62 	qchmap = ((EDMA3_CHMAP_PARSET_MASK & cfg->slot)  in qedma3_start()
64 		  (cfg->trigger_slot_word << EDMA3_CHMAP_TRIGWORD_SHIFT);  in qedma3_start()
66 	__raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum));  in qedma3_start()
69 	__raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);  in qedma3_start()
70 	__raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);  in qedma3_start()
73 	__raw_writel(1 << cfg->chnum, base + EDMA3_QEESR);  in qedma3_start()
314 void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg)  in edma3_slot_configure()  argument
320 	__raw_writel(cfg->opt, &rg->opt);  in edma3_slot_configure()
321 	__raw_writel(cfg->src, &rg->src);  in edma3_slot_configure()
322 	__raw_writel((cfg->bcnt << 16) | (cfg->acnt & 0xffff), &rg->a_b_cnt);  in edma3_slot_configure()
323 	__raw_writel(cfg->dst, &rg->dst);  in edma3_slot_configure()
324 	__raw_writel((cfg->dst_bidx << 16) |  in edma3_slot_configure()
325 		     (cfg->src_bidx & 0xffff), &rg->src_dst_bidx);  in edma3_slot_configure()
326 	__raw_writel((cfg->bcntrld << 16) |  in edma3_slot_configure()
327 		     (cfg->link & 0xffff), &rg->link_bcntrld);  in edma3_slot_configure()
328 	__raw_writel((cfg->dst_cidx << 16) |  in edma3_slot_configure()
329 		     (cfg->src_cidx & 0xffff), &rg->src_dst_cidx);  in edma3_slot_configure()
330 	__raw_writel(0xffff & cfg->ccnt, &rg->ccnt);  in edma3_slot_configure()
342 int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg)  in edma3_check_for_transfer()  argument
348 	if (cfg->complete_code < 32) {  in edma3_check_for_transfer()
351 		inum = 1 << cfg->complete_code;  in edma3_check_for_transfer()
355 		inum = 1 << (cfg->complete_code - 32);  in edma3_check_for_transfer()
374 void qedma3_stop(u32 base, struct edma3_channel_config *cfg)  in qedma3_stop()  argument
377 	__raw_writel(1 << cfg->chnum, base + EDMA3_QEECR);  in qedma3_stop()
380 	if (cfg->complete_code < 32)  in qedma3_stop()
381 		__raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);  in qedma3_stop()
383 		__raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);  in qedma3_stop()
386 	__raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);  in qedma3_stop()
387 	__raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);  in qedma3_stop()
390 	__raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum));  in qedma3_stop()