Lines Matching refs:cfg
88 const struct rockchip_combphy_cfg *cfg; member
105 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready() local
108 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
109 cfg->pipe_phy_status.bitstart); in rockchip_combphy_is_ready()
111 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); in rockchip_combphy_is_ready()
112 val = (val & mask) >> cfg->pipe_phy_status.bitstart; in rockchip_combphy_is_ready()
122 if (priv->cfg->combphy_cfg) { in rockchip_combphy_pcie_init()
123 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_pcie_init()
130 if (priv->cfg->force_det_out) { in rockchip_combphy_pcie_init()
141 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_usb3_init() local
145 ret = param_write(priv->pipe_grf, &cfg->u3otg0_port_en, false); in rockchip_combphy_usb3_init()
148 param_write(priv->pipe_grf, &cfg->u3otg1_port_en, false); in rockchip_combphy_usb3_init()
150 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rockchip_combphy_usb3_init()
154 if (cfg->u3otg0_clamp_dis.enable) in rockchip_combphy_usb3_init()
155 param_write(priv->pipe_grf, &cfg->u3otg0_clamp_dis, true); in rockchip_combphy_usb3_init()
158 if (priv->cfg->combphy_cfg) { in rockchip_combphy_usb3_init()
159 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_usb3_init()
173 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sata_init()
174 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sata_init()
188 if (priv->cfg->combphy_cfg) { in rockchip_combphy_sgmii_init()
189 ret = priv->cfg->combphy_cfg(priv); in rockchip_combphy_sgmii_init()
206 const struct rockchip_combphy_grfcfg *cfg; in rockchip_combphy_usb3_uboot_init() local
230 cfg = priv->cfg->grfcfg; in rockchip_combphy_usb3_uboot_init()
235 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_usb3_uboot_init()
236 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); in rockchip_combphy_usb3_uboot_init()
241 val == cfg->pipe_phy_status.enable, in rockchip_combphy_usb3_uboot_init()
245 param_write(priv->phy_grf, &cfg->usb_mode_set, false); in rockchip_combphy_usb3_uboot_init()
246 if (cfg->u3otg0_pipe_clk_sel.disable) in rockchip_combphy_usb3_uboot_init()
247 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, false); in rockchip_combphy_usb3_uboot_init()
253 if (cfg->u3otg0_pipe_clk_sel.disable) in rockchip_combphy_usb3_uboot_init()
254 param_write(priv->phy_grf, &cfg->u3otg0_pipe_clk_sel, true); in rockchip_combphy_usb3_uboot_init()
285 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_init() local
298 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_init()
299 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false); in rockchip_combphy_init()
312 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_exit() local
314 if (cfg->pipe_phy_grf_reset.enable) in rockchip_combphy_exit()
315 param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true); in rockchip_combphy_exit()
401 priv->cfg = phy_cfg; in rockchip_combphy_probe()
409 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3528_combphy_cfg() local
420 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3528_combphy_cfg()
421 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3528_combphy_cfg()
422 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3528_combphy_cfg()
423 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3528_combphy_cfg()
444 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3528_combphy_cfg()
445 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3528_combphy_cfg()
446 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3528_combphy_cfg()
453 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3528_combphy_cfg()
503 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3562_combphy_cfg() local
514 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3562_combphy_cfg()
515 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3562_combphy_cfg()
516 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3562_combphy_cfg()
517 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3562_combphy_cfg()
556 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3562_combphy_cfg()
557 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3562_combphy_cfg()
558 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3562_combphy_cfg()
559 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3562_combphy_cfg()
567 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3562_combphy_cfg()
589 param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); in rk3562_combphy_cfg()
646 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3568_combphy_cfg() local
657 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3568_combphy_cfg()
658 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3568_combphy_cfg()
659 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3568_combphy_cfg()
660 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3568_combphy_cfg()
699 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rk3568_combphy_cfg()
700 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3568_combphy_cfg()
701 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3568_combphy_cfg()
702 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3568_combphy_cfg()
707 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3568_combphy_cfg()
708 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3568_combphy_cfg()
709 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3568_combphy_cfg()
710 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3568_combphy_cfg()
711 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3568_combphy_cfg()
714 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
715 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
716 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
717 param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); in rk3568_combphy_cfg()
720 param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); in rk3568_combphy_cfg()
721 param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); in rk3568_combphy_cfg()
722 param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); in rk3568_combphy_cfg()
723 param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); in rk3568_combphy_cfg()
724 param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); in rk3568_combphy_cfg()
732 param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); in rk3568_combphy_cfg()
789 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3588_combphy_cfg() local
794 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3588_combphy_cfg()
795 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3588_combphy_cfg()
796 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3588_combphy_cfg()
797 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3588_combphy_cfg()
836 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3588_combphy_cfg()
837 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3588_combphy_cfg()
838 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3588_combphy_cfg()
849 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3588_combphy_cfg()
850 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3588_combphy_cfg()
851 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3588_combphy_cfg()
852 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3588_combphy_cfg()
853 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3588_combphy_cfg()
854 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3588_combphy_cfg()
865 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3588_combphy_cfg()
927 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rk3576_combphy_cfg() local
932 param_write(priv->phy_grf, &cfg->con0_for_pcie, true); in rk3576_combphy_cfg()
933 param_write(priv->phy_grf, &cfg->con1_for_pcie, true); in rk3576_combphy_cfg()
934 param_write(priv->phy_grf, &cfg->con2_for_pcie, true); in rk3576_combphy_cfg()
935 param_write(priv->phy_grf, &cfg->con3_for_pcie, true); in rk3576_combphy_cfg()
974 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rk3576_combphy_cfg()
975 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rk3576_combphy_cfg()
976 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rk3576_combphy_cfg()
987 param_write(priv->phy_grf, &cfg->con0_for_sata, true); in rk3576_combphy_cfg()
988 param_write(priv->phy_grf, &cfg->con1_for_sata, true); in rk3576_combphy_cfg()
989 param_write(priv->phy_grf, &cfg->con2_for_sata, true); in rk3576_combphy_cfg()
990 param_write(priv->phy_grf, &cfg->con3_for_sata, true); in rk3576_combphy_cfg()
991 param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); in rk3576_combphy_cfg()
992 param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); in rk3576_combphy_cfg()
1003 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rk3576_combphy_cfg()
1068 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rv1126b_combphy_cfg() local
1109 param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); in rv1126b_combphy_cfg()
1110 param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); in rv1126b_combphy_cfg()
1111 param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); in rv1126b_combphy_cfg()
1112 param_write(priv->phy_grf, &cfg->usb_mode_set, true); in rv1126b_combphy_cfg()
1120 param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); in rv1126b_combphy_cfg()