71 int cm_basic_init(const struct cm_config * const cfg)  in cm_basic_init()  argument
138 	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);  in cm_basic_init()
139 	writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);  in cm_basic_init()
140 	writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);  in cm_basic_init()
149 	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);  in cm_basic_init()
152 	writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);  in cm_basic_init()
155 	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);  in cm_basic_init()
158 	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);  in cm_basic_init()
161 	writel(cfg->cfg2fuser0clk,  in cm_basic_init()
165 	writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);  in cm_basic_init()
168 	writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);  in cm_basic_init()
171 	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);  in cm_basic_init()
173 	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);  in cm_basic_init()
176 	writel(cfg->mainnandsdmmcclk,  in cm_basic_init()
179 	writel(cfg->pernandsdmmcclk,  in cm_basic_init()
183 	writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);  in cm_basic_init()
186 	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);  in cm_basic_init()
194 	writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,  in cm_basic_init()
198 	writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,  in cm_basic_init()
202 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,  in cm_basic_init()
206 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);  in cm_basic_init()
208 	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);  in cm_basic_init()
210 	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);  in cm_basic_init()
213 	writel(cfg->perdiv, &clock_manager_base->per_pll.div);  in cm_basic_init()
215 	writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);  in cm_basic_init()
220 	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,  in cm_basic_init()
223 	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,  in cm_basic_init()
226 	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,  in cm_basic_init()
229 	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,  in cm_basic_init()
249 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|  in cm_basic_init()
262 	writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,  in cm_basic_init()
269 	ret = cm_write_with_phase(cfg->ddrdqsclk,  in cm_basic_init()
276 	ret = cm_write_with_phase(cfg->ddr2xdqsclk,  in cm_basic_init()
282 	ret = cm_write_with_phase(cfg->ddrdqclk,  in cm_basic_init()
288 	ret = cm_write_with_phase(cfg->s2fuser2clk,  in cm_basic_init()
304 	writel(cfg->persrc, &clock_manager_base->per_pll.src);  in cm_basic_init()
305 	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);  in cm_basic_init()