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Searched refs:bpp (Results 1 – 25 of 50) sorted by relevance

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/rk3399_rockchip-uboot/drivers/video/
H A Dmxsfb.c51 struct ctfb_res_modes *mode, int bpp) in mxs_lcd_init() argument
63 switch (bpp) { in mxs_lcd_init()
156 int bpp = -1; in video_hw_init() local
170 bpp = video_get_params(&mode, penv); in video_hw_init()
174 mode.xres, mode.yres, bpp); in video_hw_init()
181 switch (bpp) { in video_hw_init()
196 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp); in video_hw_init()
218 mxs_lcd_init(&panel, &mode, bpp); in video_hw_init()
H A Danx9804.h20 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
23 int bpp) {} in anx9804_init() argument
H A Dati_radeon_fb.c47 #define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ argument
49 #define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ argument
50 ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
360 void radeon_setmode_9200(int vesa_idx, int bpp) in radeon_setmode_9200() argument
369 switch (bpp) { in radeon_setmode_9200()
407 switch (bpp) { in radeon_setmode_9200()
438 switch (bpp) { in radeon_setmode_9200()
466 switch (bpp) { in radeon_setmode_9200()
500 switch (bpp) { in radeon_setmode_9200()
541 if (bpp > 8) in radeon_setmode_9200()
H A Dmb862xx.c237 int tmp, i, bpp; in card_init() local
275 bpp = vesa_modes[1].bits_per_pixel; in card_init()
278 bpp = vesa_modes[i].bits_per_pixel; in card_init()
282 bpp = video_get_params (res_mode, penv); in card_init()
299 res_mode->yres, bpp, (hsync / 1000), (vsync / 1000)); in card_init()
305 switch (bpp) { in card_init()
317 bpp); in card_init()
447 void video_hw_rectfill (unsigned int bpp, unsigned int dst_x, in video_hw_rectfill() argument
461 void video_hw_bitblt (unsigned int bpp, unsigned int src_x, in video_hw_bitblt() argument
H A Dda8xx-fb.c482 u32 bpp, u32 raster_order) in lcd_cfg_frame_buffer() argument
529 if (bpp == 24) in lcd_cfg_frame_buffer()
531 else if (bpp == 32) in lcd_cfg_frame_buffer()
537 switch (bpp) { in lcd_cfg_frame_buffer()
669 u32 bpp; in lcd_init() local
707 if (cfg->bpp <= cfg->p_disp_panel->max_bpp && in lcd_init()
708 cfg->bpp >= cfg->p_disp_panel->min_bpp) in lcd_init()
709 bpp = cfg->bpp; in lcd_init()
711 bpp = cfg->p_disp_panel->max_bpp; in lcd_init()
712 if (bpp == 12) in lcd_init()
[all …]
H A Dam335x-fb.c64 #define FBSIZE(x) ((x->hactive * x->vactive * x->bpp) >> 3)
121 switch (panel->bpp) { in am335xfb_init()
131 pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp); in am335xfb_init()
136 panel->hactive, panel->vactive, panel->bpp, in am335xfb_init()
H A Danx9804.c29 void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp) in anx9804_init() argument
37 if (bpp == 18) in anx9804_init()
H A Dbus_vcxk.c364 unsigned long bpp; in vcxk_display_bitmap() local
377 bpp = le16_to_cpu(bmp->header.bit_count); in vcxk_display_bitmap()
395 switch (bpp) { in vcxk_display_bitmap()
401 "not supported by VCxK\n", bpp); in vcxk_display_bitmap()
H A Dam335x-fb.h49 unsigned int bpp; /* bits per pixel */ member
H A Dvideomodes.c162 int bpp; in video_get_params() local
196 bpp = 24 - ((mode % 3) * 8); in video_get_params()
213 GET_OPTION ("depth:", bpp) in video_get_params()
218 return bpp; in video_get_params()
H A Dfsl_dcu_fb.c247 unsigned int bpp = BPP_24_RGB888; in layer_ctrldesc_init() local
261 bpp = BPP_16_RGB565; in layer_ctrldesc_init()
264 bpp = BPP_24_RGB888; in layer_ctrldesc_init()
267 bpp = BPP_32_ARGB8888; in layer_ctrldesc_init()
276 DCU_CTRLDESCLN_4_BPP(bpp) | in layer_ctrldesc_init()
H A Dda8xx-fb.h76 int bpp; member
H A Dtegra.c66 val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; in update_window()
84 if (win->bpp < 24) in update_window()
236 win->bpp = 32; in setup_window()
240 win->bpp = 16; in setup_window()
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dlibnsbmp.c135 bmp->bpp = read_uint16(data, 10); in bmp_info_header_parse()
141 if ((bmp->bpp != 1) && (bmp->bpp != 4) && in bmp_info_header_parse()
142 (bmp->bpp != 8) && in bmp_info_header_parse()
143 (bmp->bpp != 16) && in bmp_info_header_parse()
144 (bmp->bpp != 24) && in bmp_info_header_parse()
145 (bmp->bpp != 32)) in bmp_info_header_parse()
147 if (bmp->bpp < 16) in bmp_info_header_parse()
148 bmp->colours = (1 << bmp->bpp); in bmp_info_header_parse()
216 bmp->bpp = read_uint16(data, 14); in bmp_info_header_parse()
217 if (bmp->bpp == 0) in bmp_info_header_parse()
[all …]
H A Dbmp_helper.c146 int stride, padded_width, bpp, i, width, height; in bmpdecoder() local
161 bpp = get_unaligned_le16(&bmp->header.bit_count); in bmpdecoder()
172 switch (bpp) { in bmpdecoder()
194 bpp, 0, 0, flip); in bmpdecoder()
234 printf("unsupport bit=%d now\n", bpp); in bmpdecoder()
H A Drockchip_display.c360 bool can_direct_logo(int bpp) in can_direct_logo() argument
362 return bpp == 16 || bpp == 32; in can_direct_logo()
1032 switch (logo->bpp) { in display_logo()
1043 printf("can't support bmp bits[%d]\n", logo->bpp); in display_logo()
1056 crtc_state->xvir = ALIGN(crtc_state->src_rect.w * logo->bpp, 32) >> 5; in display_logo()
1284 logo->bpp = get_unaligned_le16(&header->bit_count); in load_bmp_logo_legacy()
1287 dst_size = logo->width * logo->height * logo->bpp >> 3; in load_bmp_logo_legacy()
1292 if (!can_direct_logo(logo->bpp)) { in load_bmp_logo_legacy()
1312 if (!can_direct_logo(logo->bpp)) { in load_bmp_logo_legacy()
1316 logo->bpp = (logo->bpp <= 16) ? 16 : logo->bpp; in load_bmp_logo_legacy()
[all …]
/rk3399_rockchip-uboot/include/
H A Dvideo_fb.h64 unsigned int bpp, /* bytes per pixel */
76 unsigned int bpp, /* bytes per pixel */
H A Dvideo_easylogo.h21 int bpp; member
/rk3399_rockchip-uboot/tools/easylogo/
H A Deasylogo.c53 int width, height, pixels, bpp, pixel_size, size, palette_size, yuyv; member
185 image->bpp = header.ImagePixelSize; in image_load_tga()
186 image->pixel_size = ((image->bpp - 1) / 8) + 1; in image_load_tga()
191 if (image->bpp != 24) { in image_load_tga()
192 printf ("Bpp not supported: %d!\n", image->bpp); in image_load_tga()
250 yuyv_image->bpp = 16; in image_rgb_to_yuyv()
286 rgb565_image->bpp = 16; in image_rgb888_to_rgb565()
424 fprintf (file, "#define DEF_%s_BPP\t\t%d\n", def_name, image->bpp); in image_save_header()
/rk3399_rockchip-uboot/board/siemens/rut/
H A Dboard.c298 .bpp = 16,
314 .bpp = 16,
330 .bpp = 24,
465 lcd_cfgs[display].bpp); in board_video_init()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-tegra20/
H A Ddisplay.h16 unsigned bpp; /* Bits per pixel */ member
/rk3399_rockchip-uboot/board/siemens/pxm2/
H A Dboard.c305 .bpp = 32,
421 da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp); in board_video_init()
423 da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp); in board_video_init()
/rk3399_rockchip-uboot/drivers/video/sunxi/
H A Dsunxi_de2.c59 int bpp, ulong address, bool is_composite) in sunxi_de2_mode_set() argument
156 switch (bpp) { in sunxi_de2_mode_set()
169 writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch); in sunxi_de2_mode_set()
/rk3399_rockchip-uboot/drivers/video/bridge/
H A Danx6345.c356 int i, bpp; in anx6345_enable() local
360 if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) { in anx6345_enable()
365 timing.hactive.typ, timing.vactive.typ, bpp); in anx6345_enable()
366 if (bpp == 6) in anx6345_enable()
/rk3399_rockchip-uboot/board/BuR/common/
H A Dcommon.c133 pnltmp.bpp = FDTPROP(PATHINF, "bpp"); in load_lcdtiming()
191 pnltmp.bpp = env_get_ulong("ds1_bpp", 10, ~0UL); in load_lcdtiming()
207 ~0UL == (pnltmp.bpp) || in load_lcdtiming()
234 pnltmp.hactive, pnltmp.vactive, pnltmp.bpp, in load_lcdtiming()

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