10017f9eeSHeiko Schocher /* 20017f9eeSHeiko Schocher * Porting to u-boot: 30017f9eeSHeiko Schocher * 40017f9eeSHeiko Schocher * (C) Copyright 2011 50017f9eeSHeiko Schocher * Stefano Babic, DENX Software Engineering, sbabic@denx.de. 60017f9eeSHeiko Schocher * 70017f9eeSHeiko Schocher * Copyright (C) 2008-2009 MontaVista Software Inc. 80017f9eeSHeiko Schocher * Copyright (C) 2008-2009 Texas Instruments Inc 90017f9eeSHeiko Schocher * 100017f9eeSHeiko Schocher * Based on the LCD driver for TI Avalanche processors written by 110017f9eeSHeiko Schocher * Ajay Singh and Shalom Hai. 120017f9eeSHeiko Schocher * 130017f9eeSHeiko Schocher * SPDX-License-Identifier: GPL-2.0+ 140017f9eeSHeiko Schocher */ 150017f9eeSHeiko Schocher 160017f9eeSHeiko Schocher #ifndef DA8XX_FB_H 170017f9eeSHeiko Schocher #define DA8XX_FB_H 180017f9eeSHeiko Schocher 190017f9eeSHeiko Schocher enum panel_type { 200017f9eeSHeiko Schocher QVGA = 0, 210017f9eeSHeiko Schocher WVGA 220017f9eeSHeiko Schocher }; 230017f9eeSHeiko Schocher 240017f9eeSHeiko Schocher enum panel_shade { 250017f9eeSHeiko Schocher MONOCHROME = 0, 260017f9eeSHeiko Schocher COLOR_ACTIVE, 270017f9eeSHeiko Schocher COLOR_PASSIVE, 280017f9eeSHeiko Schocher }; 290017f9eeSHeiko Schocher 300017f9eeSHeiko Schocher enum raster_load_mode { 310017f9eeSHeiko Schocher LOAD_DATA = 1, 320017f9eeSHeiko Schocher LOAD_PALETTE, 330017f9eeSHeiko Schocher }; 340017f9eeSHeiko Schocher 350017f9eeSHeiko Schocher struct display_panel { 360017f9eeSHeiko Schocher enum panel_type panel_type; /* QVGA */ 370017f9eeSHeiko Schocher int max_bpp; 380017f9eeSHeiko Schocher int min_bpp; 390017f9eeSHeiko Schocher enum panel_shade panel_shade; 400017f9eeSHeiko Schocher }; 410017f9eeSHeiko Schocher 420017f9eeSHeiko Schocher struct da8xx_panel { 430017f9eeSHeiko Schocher const char name[25]; /* Full name <vendor>_<model> */ 440017f9eeSHeiko Schocher unsigned short width; 450017f9eeSHeiko Schocher unsigned short height; 460017f9eeSHeiko Schocher int hfp; /* Horizontal front porch */ 470017f9eeSHeiko Schocher int hbp; /* Horizontal back porch */ 480017f9eeSHeiko Schocher int hsw; /* Horizontal Sync Pulse Width */ 490017f9eeSHeiko Schocher int vfp; /* Vertical front porch */ 500017f9eeSHeiko Schocher int vbp; /* Vertical back porch */ 510017f9eeSHeiko Schocher int vsw; /* Vertical Sync Pulse Width */ 520017f9eeSHeiko Schocher unsigned int pxl_clk; /* Pixel clock */ 530017f9eeSHeiko Schocher unsigned char invert_pxl_clk; /* Invert Pixel clock */ 540017f9eeSHeiko Schocher }; 550017f9eeSHeiko Schocher 560017f9eeSHeiko Schocher struct da8xx_lcdc_platform_data { 570017f9eeSHeiko Schocher const char manu_name[10]; 580017f9eeSHeiko Schocher void *controller_data; 590017f9eeSHeiko Schocher const char type[25]; 600017f9eeSHeiko Schocher void (*panel_power_ctrl)(int); 610017f9eeSHeiko Schocher }; 620017f9eeSHeiko Schocher 630017f9eeSHeiko Schocher struct lcd_ctrl_config { 640017f9eeSHeiko Schocher const struct display_panel *p_disp_panel; 650017f9eeSHeiko Schocher 660017f9eeSHeiko Schocher /* AC Bias Pin Frequency */ 670017f9eeSHeiko Schocher int ac_bias; 680017f9eeSHeiko Schocher 690017f9eeSHeiko Schocher /* AC Bias Pin Transitions per Interrupt */ 700017f9eeSHeiko Schocher int ac_bias_intrpt; 710017f9eeSHeiko Schocher 720017f9eeSHeiko Schocher /* DMA burst size */ 730017f9eeSHeiko Schocher int dma_burst_sz; 740017f9eeSHeiko Schocher 750017f9eeSHeiko Schocher /* Bits per pixel */ 760017f9eeSHeiko Schocher int bpp; 770017f9eeSHeiko Schocher 780017f9eeSHeiko Schocher /* FIFO DMA Request Delay */ 790017f9eeSHeiko Schocher int fdd; 800017f9eeSHeiko Schocher 810017f9eeSHeiko Schocher /* TFT Alternative Signal Mapping (Only for active) */ 820017f9eeSHeiko Schocher unsigned char tft_alt_mode; 830017f9eeSHeiko Schocher 840017f9eeSHeiko Schocher /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ 850017f9eeSHeiko Schocher unsigned char stn_565_mode; 860017f9eeSHeiko Schocher 870017f9eeSHeiko Schocher /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ 880017f9eeSHeiko Schocher unsigned char mono_8bit_mode; 890017f9eeSHeiko Schocher 900017f9eeSHeiko Schocher /* Invert line clock */ 910017f9eeSHeiko Schocher unsigned char invert_line_clock; 920017f9eeSHeiko Schocher 930017f9eeSHeiko Schocher /* Invert frame clock */ 940017f9eeSHeiko Schocher unsigned char invert_frm_clock; 950017f9eeSHeiko Schocher 960017f9eeSHeiko Schocher /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ 970017f9eeSHeiko Schocher unsigned char sync_edge; 980017f9eeSHeiko Schocher 990017f9eeSHeiko Schocher /* Horizontal and Vertical Sync: Control: 0=ignore */ 1000017f9eeSHeiko Schocher unsigned char sync_ctrl; 1010017f9eeSHeiko Schocher 1020017f9eeSHeiko Schocher /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ 1030017f9eeSHeiko Schocher unsigned char raster_order; 1040017f9eeSHeiko Schocher }; 1050017f9eeSHeiko Schocher 1060017f9eeSHeiko Schocher struct lcd_sync_arg { 1070017f9eeSHeiko Schocher int back_porch; 1080017f9eeSHeiko Schocher int front_porch; 1090017f9eeSHeiko Schocher int pulse_width; 1100017f9eeSHeiko Schocher }; 1110017f9eeSHeiko Schocher 112*765f2f08SHeiko Schocher void da8xx_video_init(const struct da8xx_panel *panel, 113*765f2f08SHeiko Schocher const struct lcd_ctrl_config *lcd_cfg, 114*765f2f08SHeiko Schocher int bits_pixel); 1150017f9eeSHeiko Schocher 1160017f9eeSHeiko Schocher #endif /* ifndef DA8XX_FB_H */ 117