13c5fabd1SHannes Petermaier /* 2*4c302b9aSHannes Schmelzer * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> - 33c5fabd1SHannes Petermaier * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 43c5fabd1SHannes Petermaier * 53c5fabd1SHannes Petermaier * SPDX-License-Identifier: GPL-2.0+ 63c5fabd1SHannes Petermaier */ 73c5fabd1SHannes Petermaier 83c5fabd1SHannes Petermaier #ifndef AM335X_FB_H 93c5fabd1SHannes Petermaier #define AM335X_FB_H 103c5fabd1SHannes Petermaier 113c5fabd1SHannes Petermaier #define HSVS_CONTROL (0x01 << 25) /* 123c5fabd1SHannes Petermaier * 0 = lcd_lp and lcd_fp are driven on 133c5fabd1SHannes Petermaier * opposite edges of pixel clock than 143c5fabd1SHannes Petermaier * the lcd_pixel_o 153c5fabd1SHannes Petermaier * 1 = lcd_lp and lcd_fp are driven 163c5fabd1SHannes Petermaier * according to bit 24 Note that this 173c5fabd1SHannes Petermaier * bit MUST be set to '0' for Passive 183c5fabd1SHannes Petermaier * Matrix displays the edge timing is 193c5fabd1SHannes Petermaier * fixed 203c5fabd1SHannes Petermaier */ 213c5fabd1SHannes Petermaier #define HSVS_RISEFALL (0x01 << 24) /* 223c5fabd1SHannes Petermaier * 0 = lcd_lp and lcd_fp are driven on 233c5fabd1SHannes Petermaier * the rising edge of pixel clock (bit 243c5fabd1SHannes Petermaier * 25 must be set to 1) 253c5fabd1SHannes Petermaier * 1 = lcd_lp and lcd_fp are driven on 263c5fabd1SHannes Petermaier * the falling edge of pixel clock (bit 273c5fabd1SHannes Petermaier * 25 must be set to 1) 283c5fabd1SHannes Petermaier */ 293c5fabd1SHannes Petermaier #define DE_INVERT (0x01 << 23) /* 303c5fabd1SHannes Petermaier * 0 = DE is low-active 313c5fabd1SHannes Petermaier * 1 = DE is high-active 323c5fabd1SHannes Petermaier */ 333c5fabd1SHannes Petermaier #define PXCLK_INVERT (0x01 << 22) /* 343c5fabd1SHannes Petermaier * 0 = pix-clk is high-active 353c5fabd1SHannes Petermaier * 1 = pic-clk is low-active 363c5fabd1SHannes Petermaier */ 373c5fabd1SHannes Petermaier #define HSYNC_INVERT (0x01 << 21) /* 383c5fabd1SHannes Petermaier * 0 = HSYNC is active high 393c5fabd1SHannes Petermaier * 1 = HSYNC is avtive low 403c5fabd1SHannes Petermaier */ 413c5fabd1SHannes Petermaier #define VSYNC_INVERT (0x01 << 20) /* 423c5fabd1SHannes Petermaier * 0 = VSYNC is active high 433c5fabd1SHannes Petermaier * 1 = VSYNC is active low 443c5fabd1SHannes Petermaier */ 453c5fabd1SHannes Petermaier 463c5fabd1SHannes Petermaier struct am335x_lcdpanel { 473c5fabd1SHannes Petermaier unsigned int hactive; /* Horizontal active area */ 483c5fabd1SHannes Petermaier unsigned int vactive; /* Vertical active area */ 493c5fabd1SHannes Petermaier unsigned int bpp; /* bits per pixel */ 503c5fabd1SHannes Petermaier unsigned int hfp; /* Horizontal front porch */ 513c5fabd1SHannes Petermaier unsigned int hbp; /* Horizontal back porch */ 523c5fabd1SHannes Petermaier unsigned int hsw; /* Horizontal Sync Pulse Width */ 533c5fabd1SHannes Petermaier unsigned int vfp; /* Vertical front porch */ 543c5fabd1SHannes Petermaier unsigned int vbp; /* Vertical back porch */ 553c5fabd1SHannes Petermaier unsigned int vsw; /* Vertical Sync Pulse Width */ 563c5fabd1SHannes Petermaier unsigned int pxl_clk_div; /* Pixel clock divider*/ 573c5fabd1SHannes Petermaier unsigned int pol; /* polarity of sync, clock signals */ 583b4e16ebSHannes Petermaier unsigned int pup_delay; /* 593b4e16ebSHannes Petermaier * time in ms after power on to 603b4e16ebSHannes Petermaier * initialization of lcd-controller 613b4e16ebSHannes Petermaier * (VCC ramp up time) 623b4e16ebSHannes Petermaier */ 633c5fabd1SHannes Petermaier unsigned int pon_delay; /* 643b4e16ebSHannes Petermaier * time in ms after initialization of 653b4e16ebSHannes Petermaier * lcd-controller (pic stabilization) 663c5fabd1SHannes Petermaier */ 673c5fabd1SHannes Petermaier void (*panel_power_ctrl)(int); /* fp for power on/off display */ 683c5fabd1SHannes Petermaier }; 693c5fabd1SHannes Petermaier 703c5fabd1SHannes Petermaier int am335xfb_init(struct am335x_lcdpanel *panel); 713c5fabd1SHannes Petermaier 723c5fabd1SHannes Petermaier #endif /* AM335X_FB_H */ 73