xref: /rk3399_rockchip-uboot/drivers/video/am335x-fb.c (revision 90aa625c9a9e1fb7a2f001fd8e50099bacaf92b8)
13c5fabd1SHannes Petermaier /*
24c302b9aSHannes Schmelzer  * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
33c5fabd1SHannes Petermaier  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
43c5fabd1SHannes Petermaier  *
53c5fabd1SHannes Petermaier  * minimal framebuffer driver for TI's AM335x SoC to be compatible with
63c5fabd1SHannes Petermaier  * Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
73c5fabd1SHannes Petermaier  *
87d045170SMartin Pietryka  * - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
93c5fabd1SHannes Petermaier  * - sets up LCD controller as in 'am335x_lcdpanel' struct given
103c5fabd1SHannes Petermaier  * - starts output DMA from gd->fb_base buffer
113c5fabd1SHannes Petermaier  *
123c5fabd1SHannes Petermaier  * SPDX-License-Identifier:	GPL-2.0+
133c5fabd1SHannes Petermaier  */
143c5fabd1SHannes Petermaier #include <common.h>
153c5fabd1SHannes Petermaier #include <asm/arch/hardware.h>
163c5fabd1SHannes Petermaier #include <lcd.h>
173c5fabd1SHannes Petermaier #include "am335x-fb.h"
183c5fabd1SHannes Petermaier 
193c5fabd1SHannes Petermaier #if !defined(LCD_CNTL_BASE)
203c5fabd1SHannes Petermaier #error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
213c5fabd1SHannes Petermaier #endif
223c5fabd1SHannes Petermaier 
233c5fabd1SHannes Petermaier 
243c5fabd1SHannes Petermaier /* LCD Control Register */
253c5fabd1SHannes Petermaier #define LCD_CLK_DIVISOR(x)			((x) << 8)
263c5fabd1SHannes Petermaier #define LCD_RASTER_MODE				0x01
273c5fabd1SHannes Petermaier /* LCD Clock Enable Register */
283c5fabd1SHannes Petermaier #define LCD_CORECLKEN				(0x01 << 0)
293c5fabd1SHannes Petermaier #define LCD_LIDDCLKEN				(0x01 << 1)
303c5fabd1SHannes Petermaier #define LCD_DMACLKEN				(0x01 << 2)
313c5fabd1SHannes Petermaier /* LCD DMA Control Register */
323c5fabd1SHannes Petermaier #define LCD_DMA_BURST_SIZE(x)			((x) << 4)
333c5fabd1SHannes Petermaier #define LCD_DMA_BURST_1				0x0
343c5fabd1SHannes Petermaier #define LCD_DMA_BURST_2				0x1
353c5fabd1SHannes Petermaier #define LCD_DMA_BURST_4				0x2
363c5fabd1SHannes Petermaier #define LCD_DMA_BURST_8				0x3
373c5fabd1SHannes Petermaier #define LCD_DMA_BURST_16			0x4
383c5fabd1SHannes Petermaier /* LCD Timing_0 Register */
393c5fabd1SHannes Petermaier #define LCD_HBPLSB(x)				((((x)-1) & 0xFF) << 24)
403c5fabd1SHannes Petermaier #define LCD_HFPLSB(x)				((((x)-1) & 0xFF) << 16)
413c5fabd1SHannes Petermaier #define LCD_HSWLSB(x)				((((x)-1) & 0x3F) << 10)
423c5fabd1SHannes Petermaier #define LCD_HORLSB(x)				(((((x) >> 4)-1) & 0x3F) << 4)
433c5fabd1SHannes Petermaier #define LCD_HORMSB(x)				(((((x) >> 4)-1) & 0x40) >> 4)
443c5fabd1SHannes Petermaier /* LCD Timing_1 Register */
453c5fabd1SHannes Petermaier #define LCD_VBP(x)				((x) << 24)
463c5fabd1SHannes Petermaier #define LCD_VFP(x)				((x) << 16)
473c5fabd1SHannes Petermaier #define LCD_VSW(x)				(((x)-1) << 10)
483c5fabd1SHannes Petermaier #define LCD_VERLSB(x)				(((x)-1) & 0x3FF)
493c5fabd1SHannes Petermaier /* LCD Timing_2 Register */
503c5fabd1SHannes Petermaier #define LCD_HSWMSB(x)				((((x)-1) & 0x3C0) << 21)
513c5fabd1SHannes Petermaier #define LCD_VERMSB(x)				((((x)-1) & 0x400) << 16)
523c5fabd1SHannes Petermaier #define LCD_HBPMSB(x)				((((x)-1) & 0x300) >> 4)
533c5fabd1SHannes Petermaier #define LCD_HFPMSB(x)				((((x)-1) & 0x300) >> 8)
543c5fabd1SHannes Petermaier #define LCD_INVMASK(x)				((x) & 0x3F00000)
553c5fabd1SHannes Petermaier /* LCD Raster Ctrl Register */
563c5fabd1SHannes Petermaier #define LCD_TFT_24BPP_MODE			(1 << 25)
573c5fabd1SHannes Petermaier #define LCD_TFT_24BPP_UNPACK			(1 << 26)
58ac5c61bfSMartin Pietryka #define LCD_PALMODE_RAWDATA			(0x02 << 20)
593c5fabd1SHannes Petermaier #define LCD_TFT_MODE				(0x01 << 7)
603c5fabd1SHannes Petermaier #define LCD_RASTER_ENABLE			(0x01 << 0)
613c5fabd1SHannes Petermaier 
623c5fabd1SHannes Petermaier 
633c5fabd1SHannes Petermaier /* Macro definitions */
643c5fabd1SHannes Petermaier #define FBSIZE(x)	((x->hactive * x->vactive * x->bpp) >> 3)
653c5fabd1SHannes Petermaier 
663c5fabd1SHannes Petermaier struct am335x_lcdhw {
673c5fabd1SHannes Petermaier 	unsigned int		pid;			/* 0x00 */
683c5fabd1SHannes Petermaier 	unsigned int		ctrl;			/* 0x04 */
693c5fabd1SHannes Petermaier 	unsigned int		gap0;			/* 0x08 */
703c5fabd1SHannes Petermaier 	unsigned int		lidd_ctrl;		/* 0x0C */
713c5fabd1SHannes Petermaier 	unsigned int		lidd_cs0_conf;		/* 0x10 */
723c5fabd1SHannes Petermaier 	unsigned int		lidd_cs0_addr;		/* 0x14 */
733c5fabd1SHannes Petermaier 	unsigned int		lidd_cs0_data;		/* 0x18 */
743c5fabd1SHannes Petermaier 	unsigned int		lidd_cs1_conf;		/* 0x1C */
753c5fabd1SHannes Petermaier 	unsigned int		lidd_cs1_addr;		/* 0x20 */
763c5fabd1SHannes Petermaier 	unsigned int		lidd_cs1_data;		/* 0x24 */
773c5fabd1SHannes Petermaier 	unsigned int		raster_ctrl;		/* 0x28 */
783c5fabd1SHannes Petermaier 	unsigned int		raster_timing0;		/* 0x2C */
793c5fabd1SHannes Petermaier 	unsigned int		raster_timing1;		/* 0x30 */
803c5fabd1SHannes Petermaier 	unsigned int		raster_timing2;		/* 0x34 */
813c5fabd1SHannes Petermaier 	unsigned int		raster_subpanel;	/* 0x38 */
823c5fabd1SHannes Petermaier 	unsigned int		raster_subpanel2;	/* 0x3C */
833c5fabd1SHannes Petermaier 	unsigned int		lcddma_ctrl;		/* 0x40 */
843c5fabd1SHannes Petermaier 	unsigned int		lcddma_fb0_base;	/* 0x44 */
853c5fabd1SHannes Petermaier 	unsigned int		lcddma_fb0_ceiling;	/* 0x48 */
863c5fabd1SHannes Petermaier 	unsigned int		lcddma_fb1_base;	/* 0x4C */
873c5fabd1SHannes Petermaier 	unsigned int		lcddma_fb1_ceiling;	/* 0x50 */
883c5fabd1SHannes Petermaier 	unsigned int		sysconfig;		/* 0x54 */
893c5fabd1SHannes Petermaier 	unsigned int		irqstatus_raw;		/* 0x58 */
903c5fabd1SHannes Petermaier 	unsigned int		irqstatus;		/* 0x5C */
913c5fabd1SHannes Petermaier 	unsigned int		irqenable_set;		/* 0x60 */
923c5fabd1SHannes Petermaier 	unsigned int		irqenable_clear;	/* 0x64 */
933c5fabd1SHannes Petermaier 	unsigned int		gap1;			/* 0x68 */
943c5fabd1SHannes Petermaier 	unsigned int		clkc_enable;		/* 0x6C */
953c5fabd1SHannes Petermaier 	unsigned int		clkc_reset;		/* 0x70 */
963c5fabd1SHannes Petermaier };
973c5fabd1SHannes Petermaier 
983c5fabd1SHannes Petermaier static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
993c5fabd1SHannes Petermaier DECLARE_GLOBAL_DATA_PTR;
1003c5fabd1SHannes Petermaier 
lcd_get_size(int * line_length)1013c5fabd1SHannes Petermaier int lcd_get_size(int *line_length)
1023c5fabd1SHannes Petermaier {
1033c5fabd1SHannes Petermaier 	*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
1043c5fabd1SHannes Petermaier 	return *line_length * panel_info.vl_row + 0x20;
1053c5fabd1SHannes Petermaier }
1063c5fabd1SHannes Petermaier 
am335xfb_init(struct am335x_lcdpanel * panel)1073c5fabd1SHannes Petermaier int am335xfb_init(struct am335x_lcdpanel *panel)
1083c5fabd1SHannes Petermaier {
1097d045170SMartin Pietryka 	u32 raster_ctrl = 0;
1107d045170SMartin Pietryka 
1113c5fabd1SHannes Petermaier 	if (0 == gd->fb_base) {
1123c5fabd1SHannes Petermaier 		printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
1133c5fabd1SHannes Petermaier 		return -1;
1143c5fabd1SHannes Petermaier 	}
1153c5fabd1SHannes Petermaier 	if (0 == panel) {
1163c5fabd1SHannes Petermaier 		printf("ERROR: missing ptr to am335x_lcdpanel!\n");
1173c5fabd1SHannes Petermaier 		return -1;
1183c5fabd1SHannes Petermaier 	}
1193c5fabd1SHannes Petermaier 
1207d045170SMartin Pietryka 	/* We can already set the bits for the raster_ctrl in this check */
1217d045170SMartin Pietryka 	switch (panel->bpp) {
1227d045170SMartin Pietryka 	case 16:
1237d045170SMartin Pietryka 		break;
1247d045170SMartin Pietryka 	case 32:
1257d045170SMartin Pietryka 		raster_ctrl |= LCD_TFT_24BPP_UNPACK;
1267d045170SMartin Pietryka 		/* fallthrough */
1277d045170SMartin Pietryka 	case 24:
1287d045170SMartin Pietryka 		raster_ctrl |= LCD_TFT_24BPP_MODE;
1297d045170SMartin Pietryka 		break;
1307d045170SMartin Pietryka 	default:
131*90aa625cSMasahiro Yamada 		pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
1327d045170SMartin Pietryka 		return -1;
1337d045170SMartin Pietryka 	}
1347d045170SMartin Pietryka 
1353c5fabd1SHannes Petermaier 	debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
1363c5fabd1SHannes Petermaier 	      panel->hactive, panel->vactive, panel->bpp,
1373c5fabd1SHannes Petermaier 	      panel->hfp, panel->hbp, panel->hsw);
1383c5fabd1SHannes Petermaier 	debug("vfp=%d,vbp=%d,vsw=%d / clk-div=%d)\n",
1393c5fabd1SHannes Petermaier 	      panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk_div);
1403c5fabd1SHannes Petermaier 	debug("using frambuffer at 0x%08x with size %d.\n",
1413c5fabd1SHannes Petermaier 	      (unsigned int)gd->fb_base, FBSIZE(panel));
1423c5fabd1SHannes Petermaier 
1433c5fabd1SHannes Petermaier 	/* palette default entry */
1443c5fabd1SHannes Petermaier 	memset((void *)gd->fb_base, 0, 0x20);
1453c5fabd1SHannes Petermaier 	*(unsigned int *)gd->fb_base = 0x4000;
1463d47b2d7SMartin Pietryka 	/* point fb behind palette */
1473d47b2d7SMartin Pietryka 	gd->fb_base += 0x20;
1483c5fabd1SHannes Petermaier 
1493b4e16ebSHannes Petermaier 	/* turn ON display through powercontrol function if accessible */
1503b4e16ebSHannes Petermaier 	if (0 != panel->panel_power_ctrl)
1513b4e16ebSHannes Petermaier 		panel->panel_power_ctrl(1);
1523b4e16ebSHannes Petermaier 
1533b4e16ebSHannes Petermaier 	debug("am335x-fb: wait for stable power ...\n");
1543b4e16ebSHannes Petermaier 	mdelay(panel->pup_delay);
1553c5fabd1SHannes Petermaier 	lcdhw->clkc_enable = LCD_CORECLKEN | LCD_LIDDCLKEN | LCD_DMACLKEN;
1563c5fabd1SHannes Petermaier 	lcdhw->raster_ctrl = 0;
1573c5fabd1SHannes Petermaier 	lcdhw->ctrl = LCD_CLK_DIVISOR(panel->pxl_clk_div) | LCD_RASTER_MODE;
1583c5fabd1SHannes Petermaier 	lcdhw->lcddma_fb0_base = gd->fb_base;
1593d47b2d7SMartin Pietryka 	lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
1603c5fabd1SHannes Petermaier 	lcdhw->lcddma_fb1_base = gd->fb_base;
1613d47b2d7SMartin Pietryka 	lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
1623c5fabd1SHannes Petermaier 	lcdhw->lcddma_ctrl = LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
1633c5fabd1SHannes Petermaier 
1643c5fabd1SHannes Petermaier 	lcdhw->raster_timing0 = LCD_HORLSB(panel->hactive) |
1653c5fabd1SHannes Petermaier 				LCD_HORMSB(panel->hactive) |
1663c5fabd1SHannes Petermaier 				LCD_HFPLSB(panel->hfp) |
1673c5fabd1SHannes Petermaier 				LCD_HBPLSB(panel->hbp) |
1683c5fabd1SHannes Petermaier 				LCD_HSWLSB(panel->hsw);
1693c5fabd1SHannes Petermaier 	lcdhw->raster_timing1 = LCD_VBP(panel->vbp) |
1703c5fabd1SHannes Petermaier 				LCD_VFP(panel->vfp) |
1713c5fabd1SHannes Petermaier 				LCD_VSW(panel->vsw) |
1723c5fabd1SHannes Petermaier 				LCD_VERLSB(panel->vactive);
1733c5fabd1SHannes Petermaier 	lcdhw->raster_timing2 = LCD_HSWMSB(panel->hsw) |
1743c5fabd1SHannes Petermaier 				LCD_VERMSB(panel->vactive) |
1753c5fabd1SHannes Petermaier 				LCD_INVMASK(panel->pol) |
1763c5fabd1SHannes Petermaier 				LCD_HBPMSB(panel->hbp) |
1773c5fabd1SHannes Petermaier 				LCD_HFPMSB(panel->hfp) |
1783c5fabd1SHannes Petermaier 				0x0000FF00;	/* clk cycles for ac-bias */
1797d045170SMartin Pietryka 	lcdhw->raster_ctrl =	raster_ctrl |
1803c5fabd1SHannes Petermaier 				LCD_PALMODE_RAWDATA |
1813c5fabd1SHannes Petermaier 				LCD_TFT_MODE |
1823c5fabd1SHannes Petermaier 				LCD_RASTER_ENABLE;
1833c5fabd1SHannes Petermaier 
1843b4e16ebSHannes Petermaier 	debug("am335x-fb: waiting picture to be stable.\n.");
1853c5fabd1SHannes Petermaier 	mdelay(panel->pon_delay);
1863c5fabd1SHannes Petermaier 
1873c5fabd1SHannes Petermaier 	return 0;
1883c5fabd1SHannes Petermaier }
189