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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h68 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
74 .refdiv = _refdiv, \
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3036.c49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
50 .refdiv = _refdiv,\
51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
H A Dclk_rv1108.c31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
32 .refdiv = _refdiv,\
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
H A Dclk_rk3399.c48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
49 .refdiv = _refdiv,\
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
H A Dclk_px30.c32 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
38 .refdiv = _refdiv, \