Home
last modified time | relevance | path

Searched refs:_postdiv1 (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h68 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
73 .postdiv1 = _postdiv1, \
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3036.c49 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
51 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
52 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
53 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
54 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
H A Dclk_rv1108.c31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
35 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
36 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
H A Dclk_rk3399.c48 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ argument
50 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
51 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2, .freq = hz};
H A Dclk_px30.c32 #define PX30_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ argument
37 .postdiv1 = _postdiv1, \