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Searched refs:PLL_VPLL (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3576.c71 [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88),
94 RK3576_CLK_DUMP(PLL_VPLL, "vpll", true),
2086 case PLL_VPLL: in rk3576_clk_get_rate()
2248 case PLL_VPLL: in rk3576_clk_set_rate()
2393 if (parent->id == PLL_VPLL) in rk3576_dclk_vop_set_parent()
2446 else if (parent->id == PLL_VPLL) in rk3576_dclk_vop_set_parent()
H A Dclk_rk3562.c51 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
91 RK3562_CLK_DUMP(PLL_VPLL, "vpll"),
1375 case PLL_VPLL: in rk3562_clk_get_rate()
1503 case PLL_VPLL: in rk3562_clk_set_rate()
H A Dclk_rk3399.c83 RK3399_CLK_DUMP(PLL_VPLL, "vpll", true),
434 case PLL_VPLL: in rk3399_pll_get_rate()
1153 case PLL_VPLL: in rk3399_clk_get_rate()
H A Dclk_rk3568.c78 [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3568_PLL_CON(40),
100 RK3568_CLK_DUMP(PLL_VPLL, "vpll", true),
2545 case PLL_VPLL: in rk3568_clk_get_rate()
2732 case PLL_VPLL: in rk3568_clk_set_rate()
3121 if (parent->id == PLL_VPLL) { in rk3568_dclk_vop_set_parent()
/rk3399_rockchip-uboot/include/dt-bindings/clock/
H A Drk3562-cru.h15 #define PLL_VPLL 3 macro
H A Drk3399-cru.h19 #define PLL_VPLL 7 macro
H A Drk3568-cru.h74 #define PLL_VPLL 5 macro
H A Drockchip,rk3576-cru.h15 #define PLL_VPLL 4 macro
/rk3399_rockchip-uboot/arch/arm/dts/
H A Drk3399.dtsi1589 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;