Home
last modified time | relevance | path

Searched refs:PLL_POSTDIV2_SHIFT (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3036.h95 PLL_POSTDIV2_SHIFT = 6, enumerator
96 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
H A Dcru_px30.h148 PLL_POSTDIV2_SHIFT = 6, enumerator
149 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
H A Dcru_rk3308.h119 PLL_POSTDIV2_SHIFT = 6, enumerator
120 PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.h34 #define PLL_POSTDIV2_SHIFT 6 macro
H A Drk628_cru.c102 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3036.c89 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
233 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
H A Dclk_rk3399.c101 PLL_POSTDIV2_SHIFT = 12, enumerator
102 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
357 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
396 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
H A Dclk_px30.c253 (rate->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
288 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c343 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | in rkdclk_init()