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Searched refs:PLL_POSTDIV1_MASK (Results 1 – 9 of 9) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3036.h83 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, enumerator
H A Dcru_px30.h135 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, enumerator
H A Dcru_rk3308.h104 PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, enumerator
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.h19 #define PLL_POSTDIV1_MASK GENMASK(14, 12) macro
H A Drk628_cru.c99 postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rk628_cru_clk_get_rate_pll()
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3036.c86 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, in rkclk_set_pll()
230 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
H A Dclk_rk3399.c104 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, enumerator
356 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
394 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | in rkclk_set_pll()
H A Dclk_px30.c250 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, in rkclk_set_pll()
285 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c339 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, in rkdclk_init()