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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 8 of 8) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rmobile/
H A Dpfc-r8a7795.c3634 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32,
3678 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32,
3722 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32,
3766 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32,
3810 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32,
3854 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32,
3898 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32,
3942 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32,
3986 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
4030 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
[all …]
H A Dpfc-r8a7796.c3812 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32,
3858 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32,
3902 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32,
3946 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32,
3990 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32,
4034 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32,
4078 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32,
4122 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32,
4166 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
4215 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
[all …]
H A Dpfc-r8a7791.c712 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
759 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
803 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
848 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
896 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
938 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
H A Dpfc-r8a7793.c1314 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
1357 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
1404 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
1445 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
1496 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
1539 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
1580 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
1612 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
1657 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
1705 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
[all …]
H A Dpfc-r8a7790.c1330 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
1366 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
1403 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
1445 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
1480 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
1519 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
1555 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
1605 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
1650 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
H A Dpfc-r8a7794.c1104 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
1163 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
1208 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
1245 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
1285 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
1326 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
1370 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
1421 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
H A Dpfc-r8a7792.c1557 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
1675 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
1734 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
/rk3399_rockchip-uboot/include/
H A Dsh_pfc.h56 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ macro