Lines Matching refs:PINMUX_CFG_REG_VAR
3634 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32,
3678 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32,
3722 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32,
3766 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32,
3810 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32,
3854 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32,
3898 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32,
3942 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32,
3986 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
4030 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
4074 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32,
4118 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32,
4162 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32,
4205 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32,
4249 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32,
4293 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32,
4337 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32,
4381 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32,
4425 { PINMUX_CFG_REG_VAR("IPSR18", 0xE6060248, 32,
4469 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32,
4529 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32,
4593 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32,