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Searched refs:M3 (Results 1 – 25 of 39) sorted by relevance

12

/rk3399_rockchip-uboot/board/ti/dra7xx/
H A Dmux_data.h16 {GPMC_AD0, (M3 | PIN_INPUT)}, /* gpmc_ad0.vout3_d0 */
17 {GPMC_AD1, (M3 | PIN_INPUT)}, /* gpmc_ad1.vout3_d1 */
18 {GPMC_AD2, (M3 | PIN_INPUT)}, /* gpmc_ad2.vout3_d2 */
19 {GPMC_AD3, (M3 | PIN_INPUT)}, /* gpmc_ad3.vout3_d3 */
20 {GPMC_AD4, (M3 | PIN_INPUT)}, /* gpmc_ad4.vout3_d4 */
21 {GPMC_AD5, (M3 | PIN_INPUT)}, /* gpmc_ad5.vout3_d5 */
22 {GPMC_AD6, (M3 | PIN_INPUT)}, /* gpmc_ad6.vout3_d6 */
23 {GPMC_AD7, (M3 | PIN_INPUT)}, /* gpmc_ad7.vout3_d7 */
24 {GPMC_AD8, (M3 | PIN_INPUT)}, /* gpmc_ad8.vout3_d8 */
25 {GPMC_AD9, (M3 | PIN_INPUT)}, /* gpmc_ad9.vout3_d9 */
[all …]
/rk3399_rockchip-uboot/board/gumstix/duovero/
H A Dduovero_mux_data.h57 {GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */
58 {GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */
59 {GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */
60 {GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */
61 {GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */
62 {GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */
63 {GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */
64 {GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */
65 {GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */
66 {GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */
[all …]
/rk3399_rockchip-uboot/board/compulab/cl-som-am57x/
H A Dmux.c89 {VIN2A_D10, (PDIS | PTU | M3) }, /* VIN2A_D10.MDIO_MCLK */
90 {VIN2A_D11, (IEN | PDIS | PTU | M3) }, /* VIN2A_D11.MDIO_D */
92 {VIN2A_D12, (IDIS | PEN | M3) }, /* VIN2A_D12.RGMII1_TXC */
93 {VIN2A_D13, (IDIS | PEN | M3) }, /* VIN2A_D13.RGMII1_TXCTL */
94 {VIN2A_D14, (IDIS | PEN | M3) }, /* VIN2A_D14.RGMII1_TXD3 */
95 {VIN2A_D15, (IDIS | PEN | M3) }, /* VIN2A_D15.RGMII1_TXD2 */
96 {VIN2A_D16, (IDIS | PEN | M3) }, /* VIN2A_D16.RGMII1_TXD1 */
97 {VIN2A_D17, (IDIS | PEN | M3) }, /* VIN2A_D17.RGMII1_TXD0 */
98 {VIN2A_D18, (IEN | PDIS | PTD | M3) }, /* VIN2A_D18.RGMII1_RXC */
99 {VIN2A_D19, (IEN | PDIS | PTD | M3) }, /* VIN2A_D19.RGMII1_RXCTL */
[all …]
/rk3399_rockchip-uboot/board/compulab/cm_t35/
H A Dcm_t35.c254 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ in cm_t3x_set_common_muxconf()
255 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ in cm_t3x_set_common_muxconf()
256 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ in cm_t3x_set_common_muxconf()
257 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ in cm_t3x_set_common_muxconf()
258 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ in cm_t3x_set_common_muxconf()
259 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ in cm_t3x_set_common_muxconf()
260 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ in cm_t3x_set_common_muxconf()
261 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ in cm_t3x_set_common_muxconf()
262 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ in cm_t3x_set_common_muxconf()
263 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ in cm_t3x_set_common_muxconf()
[all …]
/rk3399_rockchip-uboot/board/amazon/kc1/
H A Dkc1.h32 { GPMC_NCS2, (IEN | PTD | M3) }, /* gpio_52 */
82 { UNIPRO_TX1, (IEN | DIS | M3) }, /* gpio_173 */
83 { UNIPRO_TY1, (IEN | DIS | M3) }, /* gpio_174 */
86 { UNIPRO_RX0, (IEN | DIS | M3) }, /* gpio_175 */
87 { UNIPRO_RY0, (IEN | DIS | M3) }, /* gpio_176 */
88 { UNIPRO_RX1, (IEN | DIS | M3) }, /* gpio_177 */
89 { UNIPRO_RY1, (IEN | DIS | M3) }, /* gpio_178 */
/rk3399_rockchip-uboot/board/compulab/cm_t3517/
H A Dmux.c203 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/ in set_muxconf_regs()
204 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/ in set_muxconf_regs()
205 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/ in set_muxconf_regs()
206 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/ in set_muxconf_regs()
207 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/ in set_muxconf_regs()
208 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/ in set_muxconf_regs()
209 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/ in set_muxconf_regs()
210 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/ in set_muxconf_regs()
211 MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/ in set_muxconf_regs()
212 MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/ in set_muxconf_regs()
[all …]
/rk3399_rockchip-uboot/board/ti/am57xx/
H A Dmux_data.h104 {VIN2A_D12, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */
105 {VIN2A_D13, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */
106 {VIN2A_D14, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */
107 {VIN2A_D15, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */
108 {VIN2A_D16, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */
109 {VIN2A_D17, (M3 | PIN_OUTPUT | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */
110 {VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */
111 {VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */
112 {VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */
113 {VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */
[all …]
/rk3399_rockchip-uboot/board/ti/panda/
H A Dpanda.c82 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); in get_board_revision()
83 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); in get_board_revision()
94 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
96 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
98 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
112 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
147 writew((IEN | M3), in is_panda_es_rev_b3()
H A Dpanda_mux_data.h66 {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
67 {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */
68 {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */
83 {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
/rk3399_rockchip-uboot/board/quipos/cairo/
H A Dcairo.h85 MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
86 MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
87 MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
88 MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
89 MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
90 MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
91 MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
92 MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
93 MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
94 MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
[all …]
/rk3399_rockchip-uboot/board/ti/beagle/
H A Dbeagle.h263 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
264 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
265 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
266 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
267 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
268 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
269 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
270 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
271 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
272 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
[all …]
/rk3399_rockchip-uboot/board/nokia/rx51/
H A Drx51.h259 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) /*HSUSB2_DA2*/\
260 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) /*HSUSB2_DA7*/\
261 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) /*HSUSB2_DA4*/\
262 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) /*HSUSB2_DA5*/\
263 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) /*HSUSB2_DA6*/\
264 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) /*HSUSB2_DA3*/\
265 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_CLK*/\
266 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB2_STP*/\
267 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_DIR*/\
268 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) /*HSUSB2_NXT*/\
[all …]
/rk3399_rockchip-uboot/board/htkw/mcx/
H A Dmcx.h265 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
267 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
269 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
271 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
273 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
349 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
351 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
353 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
354 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
355 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
[all …]
/rk3399_rockchip-uboot/board/overo/
H A Dcommon.c212 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
213 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
214 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
215 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
216 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
217 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
233 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
234 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
235 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
236 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
[all …]
/rk3399_rockchip-uboot/board/teejet/mt_ventoux/
H A Dmt_ventoux.h121 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
349 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
351 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
353 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
354 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
355 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
356 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
357 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
358 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
359 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
[all …]
/rk3399_rockchip-uboot/board/ti/am3517crane/
H A Dam3517crane.h294 MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M3))\
295 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3))\
296 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M3))\
297 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M3))\
298 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3))\
299 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M3))\
300 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M3))\
301 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M3))\
302 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M3))\
303 MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M3))\
[all …]
/rk3399_rockchip-uboot/board/technexion/twister/
H A Dtwister.h124 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M3)) /*PWM11*/ \
347 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
349 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
351 MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M3)) \
352 MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | EN | M3)) \
353 MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M3)) \
354 MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M3)) \
355 MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M3)) \
356 MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M3)) \
357 MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M3)) \
[all …]
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-de212/
H A Dtie-asm.h81 rsr.M3 \at1 // MAC16 option
136 wsr.M3 \at1 // MAC16 option
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie-asm.h53 rsr \at2, M3
96 wsr \at2, M3
/rk3399_rockchip-uboot/board/pandora/
H A Dpandora.h286 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*USB_HOST_CLK*/\
287 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | EN | M3)) /*USB_HOST_STP*/\
288 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_DIR*/\
289 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_NXT*/\
290 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D0*/\
291 MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*USB_HOST_D1*/\
292 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*USB_HOST_D2*/\
293 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*USB_HOST_D3*/\
294 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*USB_HOST_D4*/\
295 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*USB_HOST_D5*/\
[all …]
/rk3399_rockchip-uboot/board/timll/devkit8000/
H A Ddevkit8000.h276 MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB1_STP*/\
277 MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | EN | M3)) /*HSUSB1_CLK*/\
278 MUX_VAL(CP(ETK_D0_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA0*/\
279 MUX_VAL(CP(ETK_D1_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA1*/\
280 MUX_VAL(CP(ETK_D2_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA2*/\
281 MUX_VAL(CP(ETK_D3_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA7*/\
282 MUX_VAL(CP(ETK_D4_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA4*/\
283 MUX_VAL(CP(ETK_D5_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA5*/\
284 MUX_VAL(CP(ETK_D6_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA6*/\
285 MUX_VAL(CP(ETK_D7_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_DATA3*/\
[all …]
/rk3399_rockchip-uboot/board/ti/evm/
H A Devm.h282 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)) /*HSUSB2_DATA2*/\
283 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)) /*HSUSB2_DATA7*/\
284 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)) /*HSUSB2_DATA4*/\
285 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)) /*HSUSB2_DATA5*/\
286 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)) /*HSUSB2_DATA6*/\
287 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)) /*HSUSB2_DATA3*/\
288 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
289 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
290 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_DIR*/\
291 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)) /*HSUSB2_NXT*/\
[all …]
/rk3399_rockchip-uboot/board/technexion/tao3530/
H A Dtao3530.h257 MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3)) \
258 MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3)) \
259 MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3)) \
260 MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3)) \
261 MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3)) \
262 MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3)) \
296 MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3)) \
297 MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)) \
298 MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3)) \
299 MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3)) \
[all …]
/rk3399_rockchip-uboot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie-asm.h90 rsr \at1, M3 // MAC16 option
155 wsr \at1, M3 // MAC16 option
/rk3399_rockchip-uboot/board/ti/sdp4430/
H A Dsdp4430_mux_data.h64 {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */

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