1*da188a03SChris Zankel /* 2*da188a03SChris Zankel * This header file contains assembly-language definitions (assembly 3*da188a03SChris Zankel * macros, etc.) for this specific Xtensa processor's TIE extensions 4*da188a03SChris Zankel * and options. It is customized to this Xtensa processor configuration. 5*da188a03SChris Zankel * This file is autogenerated, please do not edit. 6*da188a03SChris Zankel * 7*da188a03SChris Zankel * Copyright (C) 1999-2007 Tensilica Inc. 8*da188a03SChris Zankel * 9*da188a03SChris Zankel * SPDX-License-Identifier: GPL-2.0+ 10*da188a03SChris Zankel */ 11*da188a03SChris Zankel 12*da188a03SChris Zankel #ifndef _XTENSA_CORE_TIE_ASM_H 13*da188a03SChris Zankel #define _XTENSA_CORE_TIE_ASM_H 14*da188a03SChris Zankel 15*da188a03SChris Zankel /* Selection parameter values for save-area save/restore macros: */ 16*da188a03SChris Zankel /* Option vs. TIE: */ 17*da188a03SChris Zankel #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 18*da188a03SChris Zankel #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 19*da188a03SChris Zankel /* Whether used automatically by compiler: */ 20*da188a03SChris Zankel #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 21*da188a03SChris Zankel #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 22*da188a03SChris Zankel /* ABI handling across function calls: */ 23*da188a03SChris Zankel #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 24*da188a03SChris Zankel #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 25*da188a03SChris Zankel #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 26*da188a03SChris Zankel /* Misc */ 27*da188a03SChris Zankel #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 28*da188a03SChris Zankel 29*da188a03SChris Zankel 30*da188a03SChris Zankel 31*da188a03SChris Zankel /* Macro to save all non-coprocessor (extra) custom TIE and optional state 32*da188a03SChris Zankel * (not including zero-overhead loop registers). 33*da188a03SChris Zankel * Save area ptr (clobbered): ptr (1 byte aligned) 34*da188a03SChris Zankel * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 35*da188a03SChris Zankel */ 36*da188a03SChris Zankel .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 37*da188a03SChris Zankel xchal_sa_start \continue, \ofs 38*da188a03SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 39*da188a03SChris Zankel xchal_sa_align \ptr, 0, 1024-8, 4, 4 40*da188a03SChris Zankel rsr \at1, ACCLO // MAC16 accumulator 41*da188a03SChris Zankel rsr \at2, ACCHI 42*da188a03SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 0 43*da188a03SChris Zankel s32i \at2, \ptr, .Lxchal_ofs_ + 4 44*da188a03SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 45*da188a03SChris Zankel .endif 46*da188a03SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 47*da188a03SChris Zankel xchal_sa_align \ptr, 0, 1024-16, 4, 4 48*da188a03SChris Zankel rsr \at1, M0 // MAC16 registers 49*da188a03SChris Zankel rsr \at2, M1 50*da188a03SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 0 51*da188a03SChris Zankel s32i \at2, \ptr, .Lxchal_ofs_ + 4 52*da188a03SChris Zankel rsr \at1, M2 53*da188a03SChris Zankel rsr \at2, M3 54*da188a03SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 8 55*da188a03SChris Zankel s32i \at2, \ptr, .Lxchal_ofs_ + 12 56*da188a03SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 57*da188a03SChris Zankel .endif 58*da188a03SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 59*da188a03SChris Zankel xchal_sa_align \ptr, 0, 1024-4, 4, 4 60*da188a03SChris Zankel rsr \at1, SCOMPARE1 // conditional store option 61*da188a03SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 0 62*da188a03SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 63*da188a03SChris Zankel .endif 64*da188a03SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 65*da188a03SChris Zankel xchal_sa_align \ptr, 0, 1024-4, 4, 4 66*da188a03SChris Zankel rur \at1, THREADPTR // threadptr option 67*da188a03SChris Zankel s32i \at1, \ptr, .Lxchal_ofs_ + 0 68*da188a03SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 69*da188a03SChris Zankel .endif 70*da188a03SChris Zankel .endm // xchal_ncp_store 71*da188a03SChris Zankel 72*da188a03SChris Zankel /* Macro to save all non-coprocessor (extra) custom TIE and optional state 73*da188a03SChris Zankel * (not including zero-overhead loop registers). 74*da188a03SChris Zankel * Save area ptr (clobbered): ptr (1 byte aligned) 75*da188a03SChris Zankel * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 76*da188a03SChris Zankel */ 77*da188a03SChris Zankel .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 78*da188a03SChris Zankel xchal_sa_start \continue, \ofs 79*da188a03SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 80*da188a03SChris Zankel xchal_sa_align \ptr, 0, 1024-8, 4, 4 81*da188a03SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 0 82*da188a03SChris Zankel l32i \at2, \ptr, .Lxchal_ofs_ + 4 83*da188a03SChris Zankel wsr \at1, ACCLO // MAC16 accumulator 84*da188a03SChris Zankel wsr \at2, ACCHI 85*da188a03SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 86*da188a03SChris Zankel .endif 87*da188a03SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 88*da188a03SChris Zankel xchal_sa_align \ptr, 0, 1024-16, 4, 4 89*da188a03SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 0 90*da188a03SChris Zankel l32i \at2, \ptr, .Lxchal_ofs_ + 4 91*da188a03SChris Zankel wsr \at1, M0 // MAC16 registers 92*da188a03SChris Zankel wsr \at2, M1 93*da188a03SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 8 94*da188a03SChris Zankel l32i \at2, \ptr, .Lxchal_ofs_ + 12 95*da188a03SChris Zankel wsr \at1, M2 96*da188a03SChris Zankel wsr \at2, M3 97*da188a03SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 98*da188a03SChris Zankel .endif 99*da188a03SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 100*da188a03SChris Zankel xchal_sa_align \ptr, 0, 1024-4, 4, 4 101*da188a03SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 0 102*da188a03SChris Zankel wsr \at1, SCOMPARE1 // conditional store option 103*da188a03SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 104*da188a03SChris Zankel .endif 105*da188a03SChris Zankel .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 106*da188a03SChris Zankel xchal_sa_align \ptr, 0, 1024-4, 4, 4 107*da188a03SChris Zankel l32i \at1, \ptr, .Lxchal_ofs_ + 0 108*da188a03SChris Zankel wur \at1, THREADPTR // threadptr option 109*da188a03SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 110*da188a03SChris Zankel .endif 111*da188a03SChris Zankel .endm // xchal_ncp_load 112*da188a03SChris Zankel 113*da188a03SChris Zankel 114*da188a03SChris Zankel 115*da188a03SChris Zankel #define XCHAL_NCP_NUM_ATMPS 2 116*da188a03SChris Zankel 117*da188a03SChris Zankel 118*da188a03SChris Zankel #define XCHAL_SA_NUM_ATMPS 2 119*da188a03SChris Zankel 120*da188a03SChris Zankel #endif /*_XTENSA_CORE_TIE_ASM_H*/ 121*da188a03SChris Zankel 122