1469ec1e3SAneesh V /* 2469ec1e3SAneesh V * (C) Copyright 2010 3469ec1e3SAneesh V * Texas Instruments Incorporated, <www.ti.com> 4469ec1e3SAneesh V * 5469ec1e3SAneesh V * Balaji Krishnamoorthy <balajitk@ti.com> 6469ec1e3SAneesh V * Aneesh V <aneesh@ti.com> 7469ec1e3SAneesh V * 8*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9469ec1e3SAneesh V */ 10469ec1e3SAneesh V #ifndef _SDP4430_MUX_DATA_H 11469ec1e3SAneesh V #define _SDP4430_MUX_DATA_H 12469ec1e3SAneesh V 13469ec1e3SAneesh V #include <asm/arch/mux_omap4.h> 14469ec1e3SAneesh V 15508a58faSSricharan const struct pad_conf_entry core_padconf_array_essential[] = { 16508a58faSSricharan 17508a58faSSricharan {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ 18508a58faSSricharan {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ 19508a58faSSricharan {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ 20508a58faSSricharan {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ 21508a58faSSricharan {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ 22508a58faSSricharan {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ 23508a58faSSricharan {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ 24508a58faSSricharan {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ 25508a58faSSricharan {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ 26508a58faSSricharan {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ 27508a58faSSricharan {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ 28508a58faSSricharan {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ 29508a58faSSricharan {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ 30508a58faSSricharan {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ 31508a58faSSricharan {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ 32508a58faSSricharan {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ 33508a58faSSricharan {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ 34508a58faSSricharan {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ 35508a58faSSricharan {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ 36508a58faSSricharan {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ 37508a58faSSricharan {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ 38508a58faSSricharan {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ 39508a58faSSricharan {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ 401a89a217SSRICHARAN R {UART3_TX_IRTX, (M0)}, /* uart3_tx */ 411a89a217SSRICHARAN R {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ 421a89a217SSRICHARAN R {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ 431a89a217SSRICHARAN R {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ 441a89a217SSRICHARAN R {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ 451a89a217SSRICHARAN R {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ 461a89a217SSRICHARAN R {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ 471a89a217SSRICHARAN R {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ 481a89a217SSRICHARAN R {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ 491a89a217SSRICHARAN R {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ 501a89a217SSRICHARAN R {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ 511a89a217SSRICHARAN R {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ 52508a58faSSricharan }; 53508a58faSSricharan 54508a58faSSricharan const struct pad_conf_entry wkup_padconf_array_essential[] = { 55508a58faSSricharan 56508a58faSSricharan {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ 57508a58faSSricharan {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ 58508a58faSSricharan {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ 59508a58faSSricharan 60508a58faSSricharan }; 61508a58faSSricharan 62508a58faSSricharan const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { 63508a58faSSricharan 643acb5534SNishanth Menon {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ 65508a58faSSricharan 66508a58faSSricharan }; 67508a58faSSricharan 68469ec1e3SAneesh V #endif /* _SDP4430_MUX_DATA_H */ 69