xref: /rk3399_rockchip-uboot/board/ti/panda/panda_mux_data.h (revision c4d376fd1c2bce8d64cec0431dd3f24957b6dec4)
1469ec1e3SAneesh V /*
2469ec1e3SAneesh V  * (C) Copyright 2010
3469ec1e3SAneesh V  * Texas Instruments Incorporated, <www.ti.com>
4469ec1e3SAneesh V  *
5469ec1e3SAneesh V  *	Balaji Krishnamoorthy	<balajitk@ti.com>
6469ec1e3SAneesh V  *	Aneesh V		<aneesh@ti.com>
7469ec1e3SAneesh V  *
8*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
9469ec1e3SAneesh V  */
1043de24fdSAneesh V #ifndef _PANDA_MUX_DATA_H_
1143de24fdSAneesh V #define _PANDA_MUX_DATA_H_
12469ec1e3SAneesh V 
13469ec1e3SAneesh V #include <asm/arch/mux_omap4.h>
14469ec1e3SAneesh V 
15508a58faSSricharan 
16508a58faSSricharan const struct pad_conf_entry core_padconf_array_essential[] = {
17508a58faSSricharan 
18508a58faSSricharan {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
19508a58faSSricharan {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
20508a58faSSricharan {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
21508a58faSSricharan {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
22508a58faSSricharan {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
23508a58faSSricharan {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
24508a58faSSricharan {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
25508a58faSSricharan {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
26508a58faSSricharan {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)},	 /* sdmmc2_clk */
27508a58faSSricharan {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
28508a58faSSricharan {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)},	 /* sdmmc1_clk */
29508a58faSSricharan {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
30508a58faSSricharan {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
31508a58faSSricharan {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
32508a58faSSricharan {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
33508a58faSSricharan {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
34508a58faSSricharan {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
35508a58faSSricharan {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
36508a58faSSricharan {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
37508a58faSSricharan {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
38508a58faSSricharan {I2C1_SCL, (PTU | IEN | M0)},				/* i2c1_scl */
39508a58faSSricharan {I2C1_SDA, (PTU | IEN | M0)},				/* i2c1_sda */
40508a58faSSricharan {I2C2_SCL, (PTU | IEN | M0)},				/* i2c2_scl */
41508a58faSSricharan {I2C2_SDA, (PTU | IEN | M0)},				/* i2c2_sda */
42508a58faSSricharan {I2C3_SCL, (PTU | IEN | M0)},				/* i2c3_scl */
43508a58faSSricharan {I2C3_SDA, (PTU | IEN | M0)},				/* i2c3_sda */
44508a58faSSricharan {I2C4_SCL, (PTU | IEN | M0)},				/* i2c4_scl */
45508a58faSSricharan {I2C4_SDA, (PTU | IEN | M0)},				/* i2c4_sda */
46508a58faSSricharan {UART3_CTS_RCTX, (PTU | IEN | M0)},			/* uart3_tx */
47508a58faSSricharan {UART3_RTS_SD, (M0)},					/* uart3_rts_sd */
48508a58faSSricharan {UART3_RX_IRRX, (IEN | M0)},				/* uart3_rx */
49d2ebaa41SSRICHARAN R {UART3_TX_IRTX, (M0)},					/* uart3_tx */
50d2ebaa41SSRICHARAN R {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
51d2ebaa41SSRICHARAN R {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
52d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
53d2ebaa41SSRICHARAN R {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
54d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
55d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
56d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
57d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
58d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
59d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
60d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */
61d2ebaa41SSRICHARAN R {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat7 */
62d2ebaa41SSRICHARAN R {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_data */
63d2ebaa41SSRICHARAN R {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* usbb1_hsic_strobe */
64d2ebaa41SSRICHARAN R {USBC1_ICUSB_DP, (IEN | M0)},					/* usbc1_icusb_dp */
65d2ebaa41SSRICHARAN R {USBC1_ICUSB_DM, (IEN | M0)},					/* usbc1_icusb_dm */
66d2ebaa41SSRICHARAN R {UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
67d2ebaa41SSRICHARAN R {GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
68d2ebaa41SSRICHARAN R {FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
69508a58faSSricharan 
70508a58faSSricharan };
71508a58faSSricharan 
72508a58faSSricharan const struct pad_conf_entry wkup_padconf_array_essential[] = {
73508a58faSSricharan 
74508a58faSSricharan {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
75508a58faSSricharan {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
76d2ebaa41SSRICHARAN R {PAD1_SYS_32K, (IEN | M0)},	 /* sys_32k */
77d2ebaa41SSRICHARAN R {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
78508a58faSSricharan 
79508a58faSSricharan };
80508a58faSSricharan 
81508a58faSSricharan const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
82508a58faSSricharan 
833acb5534SNishanth Menon {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
84508a58faSSricharan 
85508a58faSSricharan };
86508a58faSSricharan 
8743de24fdSAneesh V #endif /* _PANDA_MUX_DATA_H_ */
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