| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram.h | 15 LPDDR3 = 6, enumerator
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_rk3288.c | 252 case LPDDR3: in pctl_cfg()
321 case LPDDR3: in phy_cfg()
489 if (sdram_params->base.dramtype != LPDDR3) in data_training()
529 if (sdram_params->base.dramtype != LPDDR3) in data_training()
660 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
793 (sdram_params->base.dramtype == LPDDR3 && in sdram_init()
835 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
874 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
895 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
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| H A D | Kconfig | 32 3 for DDR3, 5 for LPDDR2, 6 for LPDDR3, 7 for LPDDR4, all other
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| H A D | sdram-px30-lpddr3-detect-333.inc | 28 .dramtype = LPDDR3,
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| H A D | sdram_px30.c | 216 if ((sdram_params->base.dramtype == LPDDR3 || in set_ctl_address_map()
443 if (sdram_params->base.dramtype == LPDDR3) in sdram_init_()
444 pctl_write_mr(dram->pctl, 3, 11, 3, LPDDR3); in sdram_init_()
458 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init_()
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| H A D | sdram_rv1126.c | 555 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) in set_ctl_address_map()
801 else if (dramtype == LPDDR3) in get_ddr_drv_odt_info()
1086 if (dramtype == LPDDR3) in set_ds_odt()
1134 } else if (dramtype == LPDDR3) { in set_ds_odt()
1837 if (dramtype == LPDDR3 && mhz <= 400) { in data_training_wr()
1927 if (dramtype == LPDDR3 && mhz <= 400) { in data_training_wr()
2139 } else if (dramtype == LPDDR3) { in high_freq_training()
2630 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init_()
2631 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3); in sdram_init_()
2743 if (dram_type != LPDDR3) in dram_detect_cap()
[all …]
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| H A D | dmc_fsp.c | 395 else if (dram_type == LPDDR3) in dmc_fsp_probe()
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| H A D | sdram_rk3188.c | 431 if (sdram_params->base.dramtype != LPDDR3) in data_training()
471 if (sdram_params->base.dramtype != LPDDR3) in data_training()
607 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
779 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
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| H A D | sdram_common.c | 38 case LPDDR3: in sdram_print_dram_type()
357 } else if (dram_type == LPDDR3 || dram_type == LPDDR2) { in sdram_detect_dbw()
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| H A D | sdram_rk3399.c | 237 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
605 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
1720 } else if (sdram_params->base.dramtype == LPDDR3) { in data_training()
2115 if (sdram_params->base.dramtype == LPDDR3) { in set_cap_relate_config()
2298 if (sdram_params->base.dramtype == LPDDR3) in dram_detect_cap()
2939 (dramtype == LPDDR3 && ddr_freq > 933) || in sdram_init()
2964 if (dramtype == LPDDR3) in sdram_init()
2985 if (sdram_params->base.dramtype == LPDDR3) in sdram_init()
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| H A D | sdram_rk3328.c | 227 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) in set_ctl_address_map()
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| /rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rv1126/ |
| H A D | sdram-rv1126-lpddr3-detect-1056.inc | 28 .dramtype = LPDDR3,
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| H A D | sdram-rv1126-lpddr3-detect-528.inc | 28 .dramtype = LPDDR3,
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| H A D | sdram-rv1126-lpddr3-detect-784.inc | 28 .dramtype = LPDDR3,
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| H A D | sdram-rv1126-lpddr3-detect-396.inc | 28 .dramtype = LPDDR3,
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| H A D | sdram-rv1126-lpddr3-detect-924.inc | 28 .dramtype = LPDDR3,
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| H A D | sdram-rv1126-lpddr3-detect-664.inc | 28 .dramtype = LPDDR3,
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| H A D | sdram-rv1126-lpddr3-detect-328.inc | 28 .dramtype = LPDDR3,
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| /rk3399_rockchip-uboot/board/google/ |
| H A D | Kconfig | 51 LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
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| /rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3066/ |
| H A D | sdram_rk3066.c | 418 if (sdram_params->base.dramtype != LPDDR3) in data_training()
458 if (sdram_params->base.dramtype != LPDDR3) in data_training()
594 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
759 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
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| /rk3399_rockchip-uboot/cmd/ddr_tool/ddr_dq_eye/ |
| H A D | ddr_dq_eye.c | 259 case LPDDR3: in do_ddr_dq_eye()
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-dmc.txt | 108 DRAM type (3=DDR3, 6=LPDDR3)
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| /rk3399_rockchip-uboot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a83t.c | 446 #error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) in sunxi_dram_init()
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| H A D | Kconfig | 250 bool "LPDDR3 with Allwinner stock configuration"
253 This option is the LPDDR3 timing used by the stock boot0 by
272 Set the dram type, 3: DDR3, 7: LPDDR3
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| /rk3399_rockchip-uboot/board/hisilicon/hikey/ |
| H A D | README | 7 * 1GB 800MHz LPDDR3 DRAM
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