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Searched refs:CLK_PWM0_DIV_MASK (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3506.h267 CLK_PWM0_DIV_MASK = 0xf << CLK_PWM0_DIV_SHIFT, enumerator
H A Dcru_rv1126.h192 CLK_PWM0_DIV_MASK = 0x7f, enumerator
H A Dcru_rk3568.h159 CLK_PWM0_DIV_MASK = 0x7f, enumerator
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3506.c733 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; in rk3506_pwm_get_rate()
766 rk_clrsetreg(&cru->pmuclksel_con[0], CLK_PWM0_DIV_MASK, in rk3506_pwm_set_rate()
H A Dclk_rk3568.c293 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; in rk3568_pwm_get_pmuclk()
316 CLK_PWM0_SEL_MASK | CLK_PWM0_DIV_MASK, in rk3568_pwm_set_pmuclk()
324 CLK_PWM0_DIV_MASK | CLK_PWM0_DIV_MASK, in rk3568_pwm_set_pmuclk()
H A Dclk_rv1126.c270 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; in rv1126_pwm_get_pmuclk()
301 CLK_PWM0_DIV_MASK, 0); in rv1126_pwm_set_pmuclk()
306 CLK_PWM0_DIV_MASK, in rv1126_pwm_set_pmuclk()