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Searched refs:CCR (Results 1 – 25 of 30) sorted by relevance

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/rk3399_rockchip-uboot/arch/sh/cpu/sh4/
H A Dcache.c43 ccr = inl(CCR); in cache_control()
49 outl(CCR_CACHE_STOP, CCR); in cache_control()
51 outl(CCR_CACHE_INIT, CCR); in cache_control()
/rk3399_rockchip-uboot/doc/
H A DREADME.ne20003 that the CCR is correctly initialized.
26 - Address of the CCR (card configuration register). It could be found
32 - The value to be written in the CCR. It selects among different I/O
/rk3399_rockchip-uboot/arch/sh/include/asm/
H A Dcpu_sh7763.h12 #define CCR 0xFF00001C macro
H A Dcpu_sh7269.h6 #define CCR CCR1 macro
H A Dcpu_sh7203.h6 #define CCR CCR1 macro
H A Dcpu_sh7264.h6 #define CCR CCR1 macro
H A Dcpu_sh7706.h9 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7710.h9 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7734.h12 #define CCR 0xFF00001C macro
H A Dcpu_sh7750.h29 #define CCR 0xFF00001C macro
H A Dcpu_sh7785.h21 #define CCR 0xFF00001C macro
H A Dcpu_sh7723.h30 #define CCR 0xFF00001C macro
H A Dcpu_sh7724.h30 #define CCR 0xFF00001C macro
H A Dcpu_sh7757.h10 #define CCR 0xFF00001C macro
H A Dcpu_sh7752.h10 #define CCR 0xFF00001C macro
H A Dcpu_sh7753.h10 #define CCR 0xFF00001C macro
H A Dcpu_sh7720.h31 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7780.h29 #define CCR 0xFF00001C macro
/rk3399_rockchip-uboot/board/ms7750se/
H A Dlowlevel_init.S101 CCR_A: .long CCR
/rk3399_rockchip-uboot/board/renesas/r2dplus/
H A Dlowlevel_init.S73 CCR_A: .long CCR /* Cache Control Register */
/rk3399_rockchip-uboot/board/ms7722se/
H A Dlowlevel_init.S134 CCR_A: .long CCR
/rk3399_rockchip-uboot/board/renesas/MigoR/
H A Dlowlevel_init.S120 CCR_A: .long CCR
/rk3399_rockchip-uboot/board/renesas/ecovec/
H A Dlowlevel_init.S195 CCR_A: .long CCR
/rk3399_rockchip-uboot/board/renesas/r7780mp/
H A Dlowlevel_init.S311 CCR_A: .long CCR
/rk3399_rockchip-uboot/board/renesas/sh7753evb/
H A Dlowlevel_init.S414 CCR_A: .long CCR

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