1*99744b7eSPhil Edworthy #ifndef _ASM_CPU_SH7269_H_ 2*99744b7eSPhil Edworthy #define _ASM_CPU_SH7269_H_ 3*99744b7eSPhil Edworthy 4*99744b7eSPhil Edworthy /* Cache */ 5*99744b7eSPhil Edworthy #define CCR1 0xFFFC1000 6*99744b7eSPhil Edworthy #define CCR CCR1 7*99744b7eSPhil Edworthy 8*99744b7eSPhil Edworthy /* SCIF */ 9*99744b7eSPhil Edworthy #define SCSMR_0 0xE8007000 10*99744b7eSPhil Edworthy #define SCIF0_BASE SCSMR_0 11*99744b7eSPhil Edworthy #define SCSMR_1 0xE8007800 12*99744b7eSPhil Edworthy #define SCIF1_BASE SCSMR_1 13*99744b7eSPhil Edworthy #define SCSMR_2 0xE8008000 14*99744b7eSPhil Edworthy #define SCIF2_BASE SCSMR_2 15*99744b7eSPhil Edworthy #define SCSMR_3 0xE8008800 16*99744b7eSPhil Edworthy #define SCIF3_BASE SCSMR_3 17*99744b7eSPhil Edworthy #define SCSMR_7 0xE800A800 18*99744b7eSPhil Edworthy #define SCIF7_BASE SCSMR_7 19*99744b7eSPhil Edworthy 20*99744b7eSPhil Edworthy /* Timer(CMT) */ 21*99744b7eSPhil Edworthy #define CMSTR 0xFFFEC000 22*99744b7eSPhil Edworthy #define CMCSR_0 0xFFFEC002 23*99744b7eSPhil Edworthy #define CMCNT_0 0xFFFEC004 24*99744b7eSPhil Edworthy #define CMCOR_0 0xFFFEC006 25*99744b7eSPhil Edworthy 26*99744b7eSPhil Edworthy #endif /* _ASM_CPU_SH7269_H_ */ 27