1f3a7b953SNobuhiro Iwamatsu #ifndef _ASM_CPU_SH7706_H_ 2f3a7b953SNobuhiro Iwamatsu #define _ASM_CPU_SH7706_H_ 3f3a7b953SNobuhiro Iwamatsu 4f3a7b953SNobuhiro Iwamatsu #define CACHE_OC_NUM_WAYS 4 5f3a7b953SNobuhiro Iwamatsu #define CCR_CACHE_INIT 0x0000000D 6f3a7b953SNobuhiro Iwamatsu 7f3a7b953SNobuhiro Iwamatsu /* MMU and Cache control */ 8f3a7b953SNobuhiro Iwamatsu #define MMUCR 0xFFFFFFE0 9f3a7b953SNobuhiro Iwamatsu #define CCR 0xFFFFFFEC 10f3a7b953SNobuhiro Iwamatsu 11f3a7b953SNobuhiro Iwamatsu /* PFC */ 12f3a7b953SNobuhiro Iwamatsu #define PACR 0xA4050100 13f3a7b953SNobuhiro Iwamatsu #define PBCR 0xA4050102 14f3a7b953SNobuhiro Iwamatsu #define PCCR 0xA4050104 15f3a7b953SNobuhiro Iwamatsu #define PETCR 0xA4050106 16f3a7b953SNobuhiro Iwamatsu 17f3a7b953SNobuhiro Iwamatsu /* Port Data Registers */ 18f3a7b953SNobuhiro Iwamatsu #define PADR 0xA4050120 19f3a7b953SNobuhiro Iwamatsu #define PBDR 0xA4050122 20f3a7b953SNobuhiro Iwamatsu #define PCDR 0xA4050124 21f3a7b953SNobuhiro Iwamatsu 22f3a7b953SNobuhiro Iwamatsu /* BSC */ 23f3a7b953SNobuhiro Iwamatsu #define FRQCR 0xffffff80 24f3a7b953SNobuhiro Iwamatsu #define BCR1 0xffffff60 25f3a7b953SNobuhiro Iwamatsu #define BCR2 0xffffff62 26f3a7b953SNobuhiro Iwamatsu #define WCR1 0xffffff64 27f3a7b953SNobuhiro Iwamatsu #define WCR2 0xffffff66 28f3a7b953SNobuhiro Iwamatsu #define MCR 0xffffff68 29f3a7b953SNobuhiro Iwamatsu 30f3a7b953SNobuhiro Iwamatsu /* SDRAM controller */ 31f3a7b953SNobuhiro Iwamatsu #define DCR 0xffffff6a 32f3a7b953SNobuhiro Iwamatsu #define RTCSR 0xffffff6e 33f3a7b953SNobuhiro Iwamatsu #define RTCNT 0xffffff70 34f3a7b953SNobuhiro Iwamatsu #define RTCOR 0xffffff72 35f3a7b953SNobuhiro Iwamatsu #define RFCR 0xffffff74 36f3a7b953SNobuhiro Iwamatsu #define SDMR 0xFFFFD000 37f3a7b953SNobuhiro Iwamatsu #define CS3_R 0xFFFFE460 38f3a7b953SNobuhiro Iwamatsu 39f3a7b953SNobuhiro Iwamatsu /* SCIF */ 40f3a7b953SNobuhiro Iwamatsu #define SCSMR_2 0xA4000150 41f3a7b953SNobuhiro Iwamatsu #define SCIF0_BASE SCSMR_2 42f3a7b953SNobuhiro Iwamatsu 43f3a7b953SNobuhiro Iwamatsu /* Timer */ 44*73f35e0bSNobuhiro Iwamatsu #define TMU_BASE 0xFFFFFE90 45f3a7b953SNobuhiro Iwamatsu 46f3a7b953SNobuhiro Iwamatsu /* On chip oscillator circuits */ 47f3a7b953SNobuhiro Iwamatsu #define WTCNT 0xFFFFFF84 48f3a7b953SNobuhiro Iwamatsu #define WTCSR 0xFFFFFF86 49f3a7b953SNobuhiro Iwamatsu 50f3a7b953SNobuhiro Iwamatsu #endif /* _ASM_CPU_SH7706_H_ */ 51