12a57e7ecSNobuhiro Iwamatsu /* 22a57e7ecSNobuhiro Iwamatsu * (C) Copyright 2008, 2011 Renesas Solutions Corp. 32a57e7ecSNobuhiro Iwamatsu * 42a57e7ecSNobuhiro Iwamatsu * SH7734 Internal I/O register 52a57e7ecSNobuhiro Iwamatsu * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 72a57e7ecSNobuhiro Iwamatsu */ 82a57e7ecSNobuhiro Iwamatsu 92a57e7ecSNobuhiro Iwamatsu #ifndef _ASM_CPU_SH7734_H_ 102a57e7ecSNobuhiro Iwamatsu #define _ASM_CPU_SH7734_H_ 112a57e7ecSNobuhiro Iwamatsu 122a57e7ecSNobuhiro Iwamatsu #define CCR 0xFF00001C 132a57e7ecSNobuhiro Iwamatsu 142a57e7ecSNobuhiro Iwamatsu #define CACHE_OC_NUM_WAYS 4 152a57e7ecSNobuhiro Iwamatsu #define CCR_CACHE_INIT 0x0000090d 162a57e7ecSNobuhiro Iwamatsu 172a57e7ecSNobuhiro Iwamatsu /* SCIF */ 182a57e7ecSNobuhiro Iwamatsu #define SCIF0_BASE 0xFFE40000 192a57e7ecSNobuhiro Iwamatsu #define SCIF1_BASE 0xFFE41000 202a57e7ecSNobuhiro Iwamatsu #define SCIF2_BASE 0xFFE42000 212a57e7ecSNobuhiro Iwamatsu #define SCIF3_BASE 0xFFE43000 222a57e7ecSNobuhiro Iwamatsu #define SCIF4_BASE 0xFFE44000 232a57e7ecSNobuhiro Iwamatsu #define SCIF5_BASE 0xFFE45000 242a57e7ecSNobuhiro Iwamatsu 252a57e7ecSNobuhiro Iwamatsu /* Timer */ 2673f35e0bSNobuhiro Iwamatsu #define TMU_BASE 0xFFD80000 272a57e7ecSNobuhiro Iwamatsu 284eb0b78eSNobuhiro Iwamatsu /* PFC */ 294eb0b78eSNobuhiro Iwamatsu #define PMMR (0xFFFC0000) 304eb0b78eSNobuhiro Iwamatsu #define MODESEL0 (0xFFFC004C) 314eb0b78eSNobuhiro Iwamatsu #define MODESEL2 (MODESEL0 + 0x4) 324eb0b78eSNobuhiro Iwamatsu #define MODESEL2_INIT (0x00003000) 334eb0b78eSNobuhiro Iwamatsu 344eb0b78eSNobuhiro Iwamatsu #define IPSR0 (0xFFFC001C) 354eb0b78eSNobuhiro Iwamatsu #define IPSR1 (IPSR0 + 0x4) 364eb0b78eSNobuhiro Iwamatsu #define IPSR2 (IPSR0 + 0x8) 374eb0b78eSNobuhiro Iwamatsu #define IPSR3 (IPSR0 + 0xC) 384eb0b78eSNobuhiro Iwamatsu #define IPSR4 (IPSR0 + 0x10) 394eb0b78eSNobuhiro Iwamatsu #define IPSR5 (IPSR0 + 0x14) 404eb0b78eSNobuhiro Iwamatsu #define IPSR6 (IPSR0 + 0x18) 414eb0b78eSNobuhiro Iwamatsu #define IPSR7 (IPSR0 + 0x1C) 424eb0b78eSNobuhiro Iwamatsu #define IPSR8 (IPSR0 + 0x20) 434eb0b78eSNobuhiro Iwamatsu #define IPSR9 (IPSR0 + 0x24) 444eb0b78eSNobuhiro Iwamatsu #define IPSR10 (IPSR0 + 0x28) 454eb0b78eSNobuhiro Iwamatsu #define IPSR11 (IPSR0 + 0x2C) 464eb0b78eSNobuhiro Iwamatsu 474eb0b78eSNobuhiro Iwamatsu #define GPSR0 (0xFFFC0004) 484eb0b78eSNobuhiro Iwamatsu #define GPSR1 (GPSR0 + 0x4) 494eb0b78eSNobuhiro Iwamatsu #define GPSR2 (GPSR0 + 0x8) 504eb0b78eSNobuhiro Iwamatsu #define GPSR3 (GPSR0 + 0xC) 514eb0b78eSNobuhiro Iwamatsu #define GPSR4 (GPSR0 + 0x10) 524eb0b78eSNobuhiro Iwamatsu #define GPSR5 (GPSR0 + 0x14) 534eb0b78eSNobuhiro Iwamatsu 544eb0b78eSNobuhiro Iwamatsu 552a57e7ecSNobuhiro Iwamatsu #endif /* _ASM_CPU_SH7734_H_ */ 56