1819833afSPeter Tyser #ifndef _ASM_CPU_SH7710_H_ 2819833afSPeter Tyser #define _ASM_CPU_SH7710_H_ 3819833afSPeter Tyser 4819833afSPeter Tyser #define CACHE_OC_NUM_WAYS 4 5819833afSPeter Tyser #define CCR_CACHE_INIT 0x0000000D 6819833afSPeter Tyser 7819833afSPeter Tyser /* MMU and Cache control */ 8819833afSPeter Tyser #define MMUCR 0xFFFFFFE0 9819833afSPeter Tyser #define CCR 0xFFFFFFEC 10819833afSPeter Tyser 11819833afSPeter Tyser /* PFC */ 12819833afSPeter Tyser #define PACR 0xA4050100 13819833afSPeter Tyser #define PBCR 0xA4050102 14819833afSPeter Tyser #define PCCR 0xA4050104 15819833afSPeter Tyser #define PETCR 0xA4050106 16819833afSPeter Tyser 17819833afSPeter Tyser /* Port Data Registers */ 18819833afSPeter Tyser #define PADR 0xA4050120 19819833afSPeter Tyser #define PBDR 0xA4050122 20819833afSPeter Tyser #define PCDR 0xA4050124 21819833afSPeter Tyser 22819833afSPeter Tyser /* BSC */ 23819833afSPeter Tyser #define CMNCR 0xA4FD0000 24819833afSPeter Tyser #define CS0BCR 0xA4FD0004 25819833afSPeter Tyser #define CS2BCR 0xA4FD0008 26819833afSPeter Tyser #define CS3BCR 0xA4FD000C 27819833afSPeter Tyser #define CS4BCR 0xA4FD0010 28819833afSPeter Tyser #define CS5ABCR 0xA4FD0014 29819833afSPeter Tyser #define CS5BBCR 0xA4FD0018 30819833afSPeter Tyser #define CS6ABCR 0xA4FD001C 31819833afSPeter Tyser #define CS6BBCR 0xA4FD0020 32819833afSPeter Tyser #define CS0WCR 0xA4FD0024 33819833afSPeter Tyser #define CS2WCR 0xA4FD0028 34819833afSPeter Tyser #define CS3WCR 0xA4FD002C 35819833afSPeter Tyser #define CS4WCR 0xA4FD0030 36819833afSPeter Tyser #define CS5AWCR 0xA4FD0034 37819833afSPeter Tyser #define CS5BWCR 0xA4FD0038 38819833afSPeter Tyser #define CS6AWCR 0xA4FD003C 39819833afSPeter Tyser #define CS6BWCR 0xA4FD0040 40819833afSPeter Tyser 41819833afSPeter Tyser /* SDRAM controller */ 42819833afSPeter Tyser #define SDCR 0xA4FD0044 43819833afSPeter Tyser #define RTCSR 0xA4FD0048 44819833afSPeter Tyser #define RTCNT 0xA4FD004C 45819833afSPeter Tyser #define RTCOR 0xA4FD0050 46819833afSPeter Tyser 47819833afSPeter Tyser /* SCIF */ 48819833afSPeter Tyser #define SCSMR_0 0xA4400000 49819833afSPeter Tyser #define SCIF0_BASE SCSMR_0 50819833afSPeter Tyser #define SCSMR_0 0xA4410000 51819833afSPeter Tyser #define SCIF1_BASE SCSMR_1 52819833afSPeter Tyser 53819833afSPeter Tyser /* Timer */ 54*73f35e0bSNobuhiro Iwamatsu #define TMU_BASE 0xA412FE90 55819833afSPeter Tyser 56819833afSPeter Tyser /* On chip oscillator circuits */ 57819833afSPeter Tyser #define FRQCR 0xA415FF80 58819833afSPeter Tyser #define WTCNT 0xA415FF84 59819833afSPeter Tyser #define WTCSR 0xA415FF86 60819833afSPeter Tyser 61819833afSPeter Tyser #endif /* _ASM_CPU_SH7710_H_ */ 62