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/rk3399_ARM-atf/plat/qti/qtiseclib/src/
H A Dqtiseclib_interface_stub.c106 void qtiseclib_psci_node_on_finish(const uint8_t *states) in qtiseclib_psci_node_on_finish() argument
114 void qtiseclib_psci_node_power_off(const uint8_t *states) in qtiseclib_psci_node_power_off() argument
118 void qtiseclib_psci_node_suspend(const uint8_t *states) in qtiseclib_psci_node_suspend() argument
122 void qtiseclib_psci_node_suspend_finish(const uint8_t *states) in qtiseclib_psci_node_suspend_finish() argument
/rk3399_ARM-atf/plat/qti/qtiseclib/inc/
H A Dqtiseclib_interface.h92 void qtiseclib_psci_node_on_finish(const uint8_t *states);
94 void qtiseclib_psci_node_power_off(const uint8_t *states);
95 void qtiseclib_psci_node_suspend(const uint8_t *states);
96 void qtiseclib_psci_node_suspend_finish(const uint8_t *states);
/rk3399_ARM-atf/docs/design_documents/
H A Dpsci_osi_mode.rst20 Local power states describe power states for an individual node, and composite
21 power states describe the combined power states for an individual node and its
24 Entry into low-power states for a topology node above the core level requires
40 states, and chooses the deepest power state for a topology node that can be
49 states, and may request for a topology node to enter a low-power state when
62 power states, and doesn't account for composite power states that are shared
165 * All cores are in one of the following states:
262 * The implementation must validate that the requested power states in the
301 object with the requested states for each power level.
306 states for each power level, and returns the deepest power level that was
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/
H A Dplat_psci_handlers.c175 static bool tegra_last_cpu_in_cluster(const plat_local_state_t *states, in tegra_last_cpu_in_cluster() argument
183 target = states[pos]; in tegra_last_cpu_in_cluster()
197 static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, in tegra_get_afflvl1_pwr_state() argument
203 plat_local_state_t target = states[core_pos]; in tegra_get_afflvl1_pwr_state()
226 if (tegra_last_cpu_in_cluster(states, ncpu)) { in tegra_get_afflvl1_pwr_state()
258 const plat_local_state_t *states, in tegra_soc_get_target_pwr_state() argument
266 (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
272 target = tegra_get_afflvl1_pwr_state(states, ncpu); in tegra_soc_get_target_pwr_state()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_psci_handlers.c184 static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states, in tegra_last_on_cpu_in_cluster() argument
192 target = states[pos]; in tegra_last_on_cpu_in_cluster()
206 static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, in tegra_get_afflvl1_pwr_state() argument
210 plat_local_state_t target = states[core_pos]; in tegra_get_afflvl1_pwr_state()
217 if (tegra_last_on_cpu_in_cluster(states, ncpu)) { in tegra_get_afflvl1_pwr_state()
243 const plat_local_state_t *states, in tegra_soc_get_target_pwr_state() argument
250 if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { in tegra_soc_get_target_pwr_state()
256 target = tegra_get_afflvl1_pwr_state(states, ncpu); in tegra_soc_get_target_pwr_state()
/rk3399_ARM-atf/fdts/
H A Dmorello-fvp.dts32 idle-states {
82 cpu-idle-states = <&cpu_sleep &cluster_sleep>;
90 cpu-idle-states = <&cpu_sleep &cluster_sleep>;
98 cpu-idle-states = <&cpu_sleep &cluster_sleep>;
106 cpu-idle-states = <&cpu_sleep &cluster_sleep>;
H A Dstm32mp15xx-dhcor-avenger96.dtsi31 gpios-states = <0>;
32 states = <1800000 0x1>,
H A Dtc-base.dtsi106 idle-states {
133 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
143 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
152 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
160 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
169 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
179 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
188 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
196 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
H A Dmorello-soc.dts33 idle-states {
73 cpu-idle-states = <&cpu_sleep &cluster_sleep>;
90 cpu-idle-states = <&cpu_sleep &cluster_sleep>;
107 cpu-idle-states = <&cpu_sleep &cluster_sleep>;
124 cpu-idle-states = <&cpu_sleep &cluster_sleep>;
H A Dfvp-base-psci-common.dtsi46 idle-states {
H A Dfvp-defs-dynamiq.dtsi36 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; \
H A Dfvp-defs.dtsi48 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; \
/rk3399_ARM-atf/plat/common/
H A Dplat_psci_common.c162 const plat_local_state_t *states, in plat_get_target_pwr_state() argument
167 const plat_local_state_t *st = states; in plat_get_target_pwr_state()
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_pm.c336 const plat_local_state_t *states, in plat_get_target_pwr_state() argument
339 return tegra_soc_get_target_pwr_state(lvl, states, ncpu); in plat_get_target_pwr_state()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/
H A Dplat_psci_handlers.c102 const plat_local_state_t *states, in tegra_soc_get_target_pwr_state() argument
113 target = *(states + core_pos); in tegra_soc_get_target_pwr_state()
115 target = *(states + cpu); in tegra_soc_get_target_pwr_state()
/rk3399_ARM-atf/docs/components/
H A Dcontext-management-library.rst12 software running in various security states (Secure/Non-Secure/Realm).
14 are not banked per world. When moving between the security states it is the
21 saving and restoring of register states across the worlds.
33 security states (Non-Secure, Secure, Realm). Each world must have its
34 configuration of system registers independent of other security states to access
37 If the CPU switches across security states (for example: from Non-secure to Secure
51 unauthorized access or data corruption between the different security states.
69 RME isolates EL3 from all other Security states and moves it into its own security
71 trusted from software in Non-secure, Secure, and Realm states.
101 TF-A supports four states for feature enablement at EL3, to make them available
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H A Dgranule-protection-tables-design.rst11 Arm CCA adds two new security states for a total of four: root, realm, secure,
12 and non-secure. In addition to new security states, corresponding physical
16 .. list-table:: Security states and PAS access rights
/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-instr.rst43 power states used by the platform. The service tracks residency time and
73 The implementation provides residency statistics only for low power states,
74 and does this regardless of the entry mechanism into those states. The
H A Dpsci-performance-juno.rst25 Juno supports CPU, cluster and system power down states, corresponding to power
26 levels 0, 1 and 2 respectively. It does not support any retention states.
/rk3399_ARM-atf/plat/nvidia/tegra/include/
H A Dtegra_private.h123 const plat_local_state_t *states,
/rk3399_ARM-atf/plat/mediatek/mt8173/
H A Dplat_pm.c589 const plat_local_state_t *states, in plat_get_target_pwr_state() argument
597 temp = *states++; in plat_get_target_pwr_state()
/rk3399_ARM-atf/docs/design/
H A Dconsole-framework.rst4 The TF-A console framework is used to register consoles for different boot states
43 consoles with each having BOOT, RUNTIME, and CRASH states respectively, the boot
159 "boot" and "crash" states, this can be changed after registration using the
247 can be registered with upto three states (called the scope). These states are
/rk3399_ARM-atf/
H A Dreadme.rst8 or AArch64 execution states.
/rk3399_ARM-atf/docs/
H A Dindex.rst43 states.
/rk3399_ARM-atf/include/plat/common/
H A Dplatform.h394 const plat_local_state_t *states,

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