| /rk3399_ARM-atf/lib/zlib/ |
| H A D | inflate.c | 95 struct inflate_state FAR *state; in inflateStateCheck() local
99 state = (struct inflate_state FAR *)strm->state; in inflateStateCheck()
100 if (state == Z_NULL || state->strm != strm || in inflateStateCheck()
101 state->mode < HEAD || state->mode > SYNC) in inflateStateCheck()
107 struct inflate_state FAR *state; in inflateResetKeep() local
110 state = (struct inflate_state FAR *)strm->state; in inflateResetKeep()
111 strm->total_in = strm->total_out = state->total = 0; in inflateResetKeep()
113 if (state->wrap) /* to support ill-conceived Java test suite */ in inflateResetKeep()
114 strm->adler = state->wrap & 1; in inflateResetKeep()
115 state->mode = HEAD; in inflateResetKeep()
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| H A D | inffast.c | 51 struct inflate_state FAR *state; in inflate_fast() local
78 state = (struct inflate_state FAR *)strm->state; in inflate_fast()
85 dmax = state->dmax; in inflate_fast()
87 wsize = state->wsize; in inflate_fast()
88 whave = state->whave; in inflate_fast()
89 wnext = state->wnext; in inflate_fast()
90 window = state->window; in inflate_fast()
91 hold = state->hold; in inflate_fast()
92 bits = state->bits; in inflate_fast()
93 lcode = state->lencode; in inflate_fast()
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/ |
| H A D | mt_cpu_pm.c | 62 static void cpupm_cpu_resume_common(const struct mtk_cpupm_pwrstate *state) in cpupm_cpu_resume_common() argument
64 CPU_PM_ASSERT(state != NULL); in cpupm_cpu_resume_common()
65 mtk_cpc_core_on_hint_clr(state->info.cpuid); in cpupm_cpu_resume_common()
81 static void cpupm_cpu_resume_smp(const struct mtk_cpupm_pwrstate *state) in cpupm_cpu_resume_smp() argument
83 CPU_PM_ASSERT(state != NULL); in cpupm_cpu_resume_smp()
87 GIC_WAKEUP_IGNORE(state->info.cpuid)); in cpupm_cpu_resume_smp()
89 cpupm_cpu_resume_common(state); in cpupm_cpu_resume_smp()
92 static void cpupm_cpu_suspend_smp(const struct mtk_cpupm_pwrstate *state) in cpupm_cpu_suspend_smp() argument
96 CPU_PM_ASSERT(state != NULL); in cpupm_cpu_suspend_smp()
98 PER_CPU_PWR_CTRL(pwr_ctrl, state->info.cpuid); in cpupm_cpu_suspend_smp()
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/mcdi/ |
| H A D | mt_cpu_pm.c | 23 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
28 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
32 if (IS_SYSTEM_SUSPEND_STATE(state)) { in pwr_state_reflect()
39 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
44 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
52 static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwron() argument
57 static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwrdwn() argument
62 static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_mcusys_pwron() argument
64 if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { in pwr_mcusys_pwron()
74 const psci_power_state_t *state) in pwr_mcusys_pwron_finished() argument
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/mcdi/ |
| H A D | mt_cpu_pm.c | 23 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
28 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
32 if (IS_SYSTEM_SUSPEND_STATE(state)) { in pwr_state_reflect()
39 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
44 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
52 static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwron() argument
57 static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwrdwn() argument
62 static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_mcusys_pwron() argument
64 if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { in pwr_mcusys_pwron()
74 const psci_power_state_t *state) in pwr_mcusys_pwron_finished() argument
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/mcdi/ |
| H A D | mt_cpu_pm.c | 23 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
28 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
32 if (IS_SYSTEM_SUSPEND_STATE(state)) { in pwr_state_reflect()
39 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
44 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
52 static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwron() argument
57 static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwrdwn() argument
62 static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_mcusys_pwron() argument
64 if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) { in pwr_mcusys_pwron()
74 const psci_power_state_t *state) in pwr_mcusys_pwron_finished() argument
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8186/ |
| H A D | plat_pm.c | 41 const psci_power_state_t *state), in plat_mt_pm_invoke() argument
42 int cpu, const psci_power_state_t *state) in plat_mt_pm_invoke()
47 ret = func(cpu, state); in plat_mt_pm_invoke()
57 const psci_power_state_t *state, unsigned int req_pstate) in plat_cpu_pwrdwn_common() argument
62 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_cpu_dwn, cpu, state); in plat_cpu_pwrdwn_common()
76 const psci_power_state_t *state, unsigned int req_pstate) in plat_cpu_pwron_common() argument
81 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_cpu_on, cpu, state); in plat_cpu_pwron_common()
89 if (IS_MCUSYS_OFF_STATE(state)) { in plat_cpu_pwron_common()
104 const psci_power_state_t *state, unsigned int req_pstate) in plat_cluster_pwrdwn_common() argument
109 if (plat_mt_pm_invoke(plat_mt_pm->pwr_cluster_dwn, cpu, state) != 0) { in plat_cluster_pwrdwn_common()
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| /rk3399_ARM-atf/plat/mediatek/mt8195/ |
| H A D | plat_pm.c | 63 const psci_power_state_t *state, unsigned int req_pstate) in plat_cpu_pwrdwn_common() argument
67 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); in plat_cpu_pwrdwn_common()
81 const psci_power_state_t *state, unsigned int req_pstate) in plat_cpu_pwron_common() argument
85 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); in plat_cpu_pwron_common()
96 if (IS_MCUSYS_OFF_STATE(state)) { in plat_cpu_pwron_common()
112 const psci_power_state_t *state, unsigned int req_pstate) in plat_cluster_pwrdwn_common() argument
116 if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) { in plat_cluster_pwrdwn_common()
127 const psci_power_state_t *state, unsigned int req_pstate) in plat_cluster_pwron_common() argument
131 if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) { in plat_cluster_pwron_common()
145 const psci_power_state_t *state, unsigned int req_pstate) in plat_mcusys_pwrdwn_common() argument
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8192/ |
| H A D | plat_pm.c | 63 const psci_power_state_t *state, unsigned int req_pstate) in plat_cpu_pwrdwn_common() argument
67 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); in plat_cpu_pwrdwn_common()
83 const psci_power_state_t *state, unsigned int req_pstate) in plat_cpu_pwron_common() argument
87 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); in plat_cpu_pwron_common()
95 if (IS_MCUSYS_OFF_STATE(state)) { in plat_cpu_pwron_common()
114 const psci_power_state_t *state, unsigned int req_pstate) in plat_cluster_pwrdwn_common() argument
118 if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) { in plat_cluster_pwrdwn_common()
129 const psci_power_state_t *state, unsigned int req_pstate) in plat_cluster_pwron_common() argument
133 if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) { in plat_cluster_pwron_common()
147 const psci_power_state_t *state, unsigned int req_pstate) in plat_mcusys_pwrdwn_common() argument
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| /rk3399_ARM-atf/drivers/renesas/common/iic_dvfs/ |
| H A D | iic_dvfs.c | 97 IIC_DVFS_FUNC(check_error, enum dvfs_state_t *state, uint32_t *err, uint8_t mode) in IIC_DVFS_FUNC() argument
118 if (*state == DVFS_SET_SLAVE) { in IIC_DVFS_FUNC()
153 *state = DVFS_START; in IIC_DVFS_FUNC()
183 *state = DVFS_START; in IIC_DVFS_FUNC()
188 IIC_DVFS_FUNC(start, enum dvfs_state_t *state) in IIC_DVFS_FUNC() argument
234 *state = DVFS_SET_SLAVE; in IIC_DVFS_FUNC()
239 IIC_DVFS_FUNC(set_slave, enum dvfs_state_t *state, uint32_t *err, uint8_t slave) in IIC_DVFS_FUNC() argument
245 result = dvfs_check_error(state, err, DVFS_WRITE_MODE); in IIC_DVFS_FUNC()
261 *state = DVFS_WRITE_ADDR; in IIC_DVFS_FUNC()
266 IIC_DVFS_FUNC(write_addr, enum dvfs_state_t *state, uint32_t *err, uint8_t reg_addr) in IIC_DVFS_FUNC() argument
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| H A D | nvg.c | 19 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) in nvg_enter_cstate() argument
27 if ((state != TEGRA_ARI_CORE_C0) && (state != TEGRA_ARI_CORE_C1) && in nvg_enter_cstate()
28 (state != TEGRA_ARI_CORE_C6) && (state != TEGRA_ARI_CORE_C7)) { in nvg_enter_cstate()
29 ERROR("%s: unknown cstate (%d)\n", __func__, state); in nvg_enter_cstate()
37 write_actlr_el1(val | (uint64_t)state); in nvg_enter_cstate()
113 uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state) in nvg_read_cstate_stats() argument
120 if (state == 0U) { in nvg_read_cstate_stats()
130 (uint64_t)state)); in nvg_read_cstate_stats()
137 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) in nvg_write_cstate_stats() argument
149 val = ((uint64_t)stats << MCE_CSTATE_STATS_TYPE_SHIFT) | state; in nvg_write_cstate_stats()
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| /rk3399_ARM-atf/plat/mediatek/mt8195/include/ |
| H A D | plat_mtk_lpm.h | 28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
35 const psci_power_state_t *state);
37 const psci_power_state_t *state);
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
41 const psci_power_state_t *state);
43 const psci_power_state_t *state);
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| /rk3399_ARM-atf/plat/mediatek/mt8192/include/ |
| H A D | plat_mtk_lpm.h | 28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
35 const psci_power_state_t *state);
37 const psci_power_state_t *state);
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
41 const psci_power_state_t *state);
43 const psci_power_state_t *state);
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| /rk3399_ARM-atf/plat/intel/soc/common/lib/sha/ |
| H A D | sha.c | 47 ctx->state[0] = SHA384_H0; in sha384_init()
48 ctx->state[1] = SHA384_H1; in sha384_init()
49 ctx->state[2] = SHA384_H2; in sha384_init()
50 ctx->state[3] = SHA384_H3; in sha384_init()
51 ctx->state[4] = SHA384_H4; in sha384_init()
52 ctx->state[5] = SHA384_H5; in sha384_init()
53 ctx->state[6] = SHA384_H6; in sha384_init()
54 ctx->state[7] = SHA384_H7; in sha384_init()
69 PUT_UINT64_BE(ctx->state[i], digest, i * 8); in sha384_finish()
101 ctx->state[0] = SHA512_H0; in sha512_init()
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| /rk3399_ARM-atf/lib/extensions/tcr/ |
| H A D | tcr2.c | 15 el3_state_t *state; in tcr2_enable() local
17 state = get_el3state_ctx(ctx); in tcr2_enable()
23 reg = read_ctx_reg(state, CTX_SCR_EL3); in tcr2_enable()
25 write_ctx_reg(state, CTX_SCR_EL3, reg); in tcr2_enable()
31 el3_state_t *state; in tcr2_disable() local
33 state = get_el3state_ctx(ctx); in tcr2_disable()
39 reg = read_ctx_reg(state, CTX_SCR_EL3); in tcr2_disable()
41 write_ctx_reg(state, CTX_SCR_EL3, reg); in tcr2_disable()
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| /rk3399_ARM-atf/plat/mediatek/mt8186/include/ |
| H A D | plat_mtk_lpm.h | 28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
35 const psci_power_state_t *state);
37 const psci_power_state_t *state);
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
41 const psci_power_state_t *state);
43 const psci_power_state_t *state);
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| /rk3399_ARM-atf/services/spd/opteed/ |
| H A D | opteed_pm.c | 35 if (get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_UNKNOWN) { in opteed_cpu_off_handler()
40 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); in opteed_cpu_off_handler()
57 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_OFF); in opteed_cpu_off_handler()
72 if (get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_UNKNOWN) { in opteed_cpu_suspend_handler()
77 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); in opteed_cpu_suspend_handler()
94 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_SUSPEND); in opteed_cpu_suspend_handler()
111 assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_OFF || in opteed_cpu_on_finish_handler()
112 get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_UNKNOWN); in opteed_cpu_on_finish_handler()
132 set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); in opteed_cpu_on_finish_handler()
149 if (get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_UNKNOWN) { in opteed_cpu_suspend_finish_handler()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/ |
| H A D | mt_cpu_pm.c | 222 static void cpupm_cpu_resume_common(const struct mtk_cpupm_pwrstate *state) in cpupm_cpu_resume_common() argument
224 CPU_PM_ASSERT(state); in cpupm_cpu_resume_common()
225 mtk_cpc_core_on_hint_clr(state->info.cpuid); in cpupm_cpu_resume_common()
226 cpupm_cpu_ildo_state_valid(state->info.cpuid); in cpupm_cpu_resume_common()
235 const struct mtk_cpupm_pwrstate *state, in cpupm_cpu_smp_afflv() argument
265 void cpupm_cpu_resume_smp(const struct mtk_cpupm_pwrstate *state) in cpupm_cpu_resume_smp() argument
267 CPU_PM_ASSERT(state); in cpupm_cpu_resume_smp()
269 cpupm_cpu_resume_common(state); in cpupm_cpu_resume_smp()
271 cpu_stage[state->info.cpuid].cpu_status &= ~PER_CPU_STATUS_HOTPLUG; in cpupm_cpu_resume_smp()
275 state, in cpupm_cpu_resume_smp()
[all …]
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| /rk3399_ARM-atf/lib/extensions/sme/ |
| H A D | sme.c | 20 el3_state_t *state; in sme_enable() local
23 state = get_el3state_ctx(context); in sme_enable()
26 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_enable()
28 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_enable()
81 el3_state_t *state; in sme_disable() local
84 state = get_el3state_ctx(context); in sme_disable()
87 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_disable()
89 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_disable()
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| /rk3399_ARM-atf/drivers/renesas/common/emmc/ |
| H A D | emmc_cmd.c | 203 EMMC_INT_STATE state; in emmc_exec_cmd() local
223 state = ESTATE_BEGIN; in emmc_exec_cmd()
232 while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) { in emmc_exec_cmd()
240 switch (state) { in emmc_exec_cmd()
256 state = ESTATE_ISSUE_CMD; in emmc_exec_cmd()
268 state = ESTATE_NON_RESP_CMD; in emmc_exec_cmd()
270 state = ESTATE_RCV_RESP; in emmc_exec_cmd()
285 state = ESTATE_ERROR; in emmc_exec_cmd()
290 state = ESTATE_ERROR; in emmc_exec_cmd()
293 state = ESTATE_END; in emmc_exec_cmd()
[all …]
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| /rk3399_ARM-atf/services/std_svc/sdei/ |
| H A D | sdei_intr_mgmt.c | 66 const sdei_cpu_state_t *state = &cpu_state[errstat]; in sdei_is_target_pe_masked() local
67 return state->pe_masked; in sdei_is_target_pe_masked()
75 sdei_cpu_state_t *state = sdei_get_this_pe_state(); in sdei_pe_mask() local
81 if (!state->pe_masked) { in sdei_pe_mask()
82 state->pe_masked = true; in sdei_pe_mask()
94 sdei_cpu_state_t *state = sdei_get_this_pe_state(); in sdei_pe_unmask() local
103 if (state->pending_enables) { in sdei_pe_unmask()
123 state->pending_enables = false; in sdei_pe_unmask()
124 state->pe_masked = false; in sdei_pe_unmask()
130 sdei_cpu_state_t *state = sdei_get_this_pe_state(); in push_dispatch() local
[all …]
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/armv8_2/ |
| H A D | pwr_ctrl.c | 81 struct mtk_cpupm_pwrstate *state) in get_mediatek_pstate() argument
84 return mtk_cpu_pwr.ops->get_pstate(domain, psci_state, state); in get_mediatek_pstate()
104 static void armv8_2_mcusys_pwr_on_common(const struct mtk_cpupm_pwrstate *state) in armv8_2_mcusys_pwr_on_common() argument
114 mtk_cpu_pwr.ops->mcusys_resume(state); in armv8_2_mcusys_pwr_on_common()
119 static void armv8_2_mcusys_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state) in armv8_2_mcusys_pwr_dwn_common() argument
126 mtk_cpu_pwr.ops->mcusys_suspend(state); in armv8_2_mcusys_pwr_dwn_common()
131 static void armv8_2_cluster_pwr_on_common(const struct mtk_cpupm_pwrstate *state) in armv8_2_cluster_pwr_on_common() argument
140 mtk_cpu_pwr.ops->cluster_resume(state); in armv8_2_cluster_pwr_on_common()
145 static void armv8_2_cluster_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state) in armv8_2_cluster_pwr_dwn_common() argument
148 mtk_cpu_pwr.ops->cluster_suspend(state); in armv8_2_cluster_pwr_dwn_common()
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| /rk3399_ARM-atf/plat/imx/imx8m/include/ |
| H A D | imx8m_psci.h | 10 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) argument
11 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) argument
12 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) argument
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| /rk3399_ARM-atf/plat/nxp/common/psci/ |
| H A D | plat_psci.c | 169 static void _pwr_suspend(const psci_power_state_t *state) in _pwr_suspend() argument
175 if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend()
183 } else if (state->pwr_domain_state[PLAT_MAX_LVL] in _pwr_suspend()
194 else if (state->pwr_domain_state[PLAT_CLSTR_LVL] == in _pwr_suspend()
205 else if (state->pwr_domain_state[PLAT_CLSTR_LVL] == in _pwr_suspend()
216 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend()
227 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) { in _pwr_suspend()
241 static void _pwr_suspend_finish(const psci_power_state_t *state) in _pwr_suspend_finish() argument
248 if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend_finish()
258 } else if (state->pwr_domain_state[PLAT_MAX_LVL] in _pwr_suspend_finish()
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| /rk3399_ARM-atf/plat/imx/imx9/common/include/ |
| H A D | imx9_psci_common.h | 14 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) argument
15 #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) argument
16 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) argument
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