11da57e54SGarmin.Chang /* 21da57e54SGarmin.Chang * Copyright (c) 2021, MediaTek Inc. All rights reserved. 31da57e54SGarmin.Chang * 41da57e54SGarmin.Chang * SPDX-License-Identifier: BSD-3-Clause 51da57e54SGarmin.Chang */ 61da57e54SGarmin.Chang 71da57e54SGarmin.Chang #ifndef PLAT_MTK_LPM_H 81da57e54SGarmin.Chang #define PLAT_MTK_LPM_H 91da57e54SGarmin.Chang 101da57e54SGarmin.Chang #include <lib/psci/psci.h> 111da57e54SGarmin.Chang #include <lib/utils_def.h> 121da57e54SGarmin.Chang 131da57e54SGarmin.Chang #define MT_IRQ_REMAIN_MAX U(32) 141da57e54SGarmin.Chang #define MT_IRQ_REMAIN_CAT_LOG BIT(31) 151da57e54SGarmin.Chang 161da57e54SGarmin.Chang struct mt_irqremain { 171da57e54SGarmin.Chang unsigned int count; 181da57e54SGarmin.Chang unsigned int irqs[MT_IRQ_REMAIN_MAX]; 191da57e54SGarmin.Chang unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX]; 201da57e54SGarmin.Chang unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX]; 211da57e54SGarmin.Chang }; 221da57e54SGarmin.Chang 231da57e54SGarmin.Chang #define PLAT_RC_STATUS_READY BIT(0) 241da57e54SGarmin.Chang #define PLAT_RC_STATUS_FEATURE_EN BIT(1) 251da57e54SGarmin.Chang #define PLAT_RC_STATUS_UART_NONSLEEP BIT(31) 261da57e54SGarmin.Chang 271da57e54SGarmin.Chang struct mt_lpm_tz { 281da57e54SGarmin.Chang int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state); 291da57e54SGarmin.Chang int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state); 301da57e54SGarmin.Chang 311da57e54SGarmin.Chang int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state); 321da57e54SGarmin.Chang int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state); 331da57e54SGarmin.Chang 341da57e54SGarmin.Chang int (*pwr_cluster_on)(unsigned int cpu, 351da57e54SGarmin.Chang const psci_power_state_t *state); 361da57e54SGarmin.Chang int (*pwr_cluster_dwn)(unsigned int cpu, 371da57e54SGarmin.Chang const psci_power_state_t *state); 381da57e54SGarmin.Chang 391da57e54SGarmin.Chang int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state); 401da57e54SGarmin.Chang int (*pwr_mcusys_on_finished)(unsigned int cpu, 411da57e54SGarmin.Chang const psci_power_state_t *state); 421da57e54SGarmin.Chang int (*pwr_mcusys_dwn)(unsigned int cpu, 431da57e54SGarmin.Chang const psci_power_state_t *state); 441da57e54SGarmin.Chang }; 451da57e54SGarmin.Chang 461da57e54SGarmin.Chang const struct mt_lpm_tz *mt_plat_cpu_pm_init(void); 47*7ac6a76cSjason-ch chen int plat_mt_pm_register(struct mt_lpm_tz *mt_pm); 481da57e54SGarmin.Chang 491da57e54SGarmin.Chang #endif /* PLAT_MTK_LPM_H */ 50