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Searched refs:shift (Results 1 – 25 of 43) sorted by relevance

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/rk3399_ARM-atf/drivers/rpi3/gpio/
H A Drpi3_gpio.c49 int shift = 3 * (gpio % 10); in rpi3_gpio_get_select() local
53 ret = (sel >> shift) & 0x07; in rpi3_gpio_get_select()
74 int shift = 3 * (gpio % 10); in rpi3_gpio_set_select() local
77 uint32_t mask = U(0x07) << shift; in rpi3_gpio_set_select()
79 sel = (sel & (~mask)) | ((fsel << shift) & mask); in rpi3_gpio_set_select()
110 int shift = gpio % 32; in rpi3_gpio_get_value() local
114 if ((value >> shift) & 0x01) in rpi3_gpio_get_value()
122 int shift = gpio % 32; in rpi3_gpio_set_value() local
128 mmio_write_32(reg_clr, U(1) << shift); in rpi3_gpio_set_value()
131 mmio_write_32(reg_set, U(1) << shift); in rpi3_gpio_set_value()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/pmic/mt6363/
H A Dmt6363_psc.c25 static int mt6363_psc_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift) in mt6363_psc_read_field() argument
38 rdata &= (mask << shift); in mt6363_psc_read_field()
39 *val = (rdata >> shift); in mt6363_psc_read_field()
44 static int mt6363_psc_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift) in mt6363_psc_write_field() argument
55 org &= ~(mask << shift); in mt6363_psc_write_field()
56 org |= (val << shift); in mt6363_psc_write_field()
/rk3399_ARM-atf/plat/mediatek/include/drivers/pmic/
H A Dpmic_psc.h26 int (*read_field)(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
27 int (*write_field)(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
32 #define PMIC_PSC_REG(_reg_name, addr, shift) \ argument
36 .reg_shift = shift, \
/rk3399_ARM-atf/drivers/st/etzpc/
H A Detzpc.c97 uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT; in etzpc_configure_decprot() local
103 (uint32_t)ETZPC_DECPROT0_MASK << shift, in etzpc_configure_decprot()
104 masked_decprot << shift); in etzpc_configure_decprot()
115 uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT; in etzpc_get_decprot() local
121 value = (mmio_read_32(base_decprot + ETZPC_DECPROT0) >> shift) & in etzpc_get_decprot()
134 uint32_t shift = BIT(decprot_id % IDS_PER_DECPROT_LOCK_REGS); in etzpc_lock_decprot() local
139 mmio_write_32(base_decprot + ETZPC_DECPROT_LOCK0, shift); in etzpc_lock_decprot()
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.h96 #define regs_update_bit_set(addr, shift) \ argument
97 regs_update_bits((addr), 0x1, 0x1, (shift))
98 #define regs_update_bit_clr(addr, shift) \ argument
99 regs_update_bits((addr), 0x0, 0x1, (shift))
102 uint32_t mask, uint32_t shift);
H A Dsoc.c91 uint32_t mask, uint32_t shift) in regs_update_bits() argument
97 tmp = orig & ~(mask << shift); in regs_update_bits()
98 tmp |= (val & mask) << shift; in regs_update_bits()
/rk3399_ARM-atf/plat/rockchip/common/include/
H A Dplat_private.h55 #define BITS_SHIFT(bits, shift) ((bits) << (shift)) argument
59 #define BITS_WITH_WMASK(bits, msk, shift)\ argument
60 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT)))
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.h131 #define regs_updata_bit_set(addr, shift) \ argument
132 regs_updata_bits((addr), 0x1, 0x1, (shift))
133 #define regs_updata_bit_clr(addr, shift) \ argument
134 regs_updata_bits((addr), 0x0, 0x1, (shift))
137 uint32_t mask, uint32_t shift);
H A Dsoc.c111 uint32_t mask, uint32_t shift) in regs_updata_bits() argument
117 tmp = orig & ~(mask << shift); in regs_updata_bits()
118 tmp |= (val & mask) << shift; in regs_updata_bits()
/rk3399_ARM-atf/drivers/renesas/common/ddr/
H A Ddram_sub_func.c41 uint32_t shift; in rcar_dram_get_boot_status() local
46 shift = GPIO_BKUP_TRG_SHIFT_CONDOR; in rcar_dram_get_boot_status()
49 shift = GPIO_BKUP_TRG_SHIFT_EBISU; in rcar_dram_get_boot_status()
52 shift = GPIO_BKUP_TRG_SHIFT_SALVATOR; in rcar_dram_get_boot_status()
57 if (reg_data & BIT(shift)) in rcar_dram_get_boot_status()
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_ioctl.c263 uint32_t shift; in pm_ioctl_sd_set_tapdelay() local
268 shift = 0; in pm_ioctl_sd_set_tapdelay()
271 shift = ZYNQMP_SD_TAP_OFFSET; in pm_ioctl_sd_set_tapdelay()
291 (uint64_t)(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), in pm_ioctl_sd_set_tapdelay()
292 (ZYNQMP_SD_ITAPCHGWIN << shift), in pm_ioctl_sd_set_tapdelay()
302 shift), 0, flag); in pm_ioctl_sd_set_tapdelay()
306 shift), (uint64_t)(ZYNQMP_SD_ITAPDLYENA << in pm_ioctl_sd_set_tapdelay()
307 shift), flag); in pm_ioctl_sd_set_tapdelay()
315 (uint64_t)(ZYNQMP_SD_ITAPDLYSEL_MASK << shift), in pm_ioctl_sd_set_tapdelay()
316 (value << shift), in pm_ioctl_sd_set_tapdelay()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8173/drivers/spm/
H A Dspm_mcdi.c410 unsigned int pwr_status, shift, i, flag = 0; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off() local
419 shift = i + PCM_MCDI_CA72_PWRSTA_SHIFT; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
420 flag |= (pwr_status & (1 << shift)) >> shift; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
429 shift = i + PCM_MCDI_CA53_PWRSTA_SHIFT; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
430 flag |= (pwr_status & (1 << shift)) >> shift; in spm_mcdi_set_cputop_pwrctrl_for_cluster_off()
/rk3399_ARM-atf/plat/socionext/uniphier/
H A Duniphier_soc_info.c16 unsigned int shift) in uniphier_get_revision_field() argument
25 return (mmio_read_32(reg) >> shift) & mask; in uniphier_get_revision_field()
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_ammu.h115 #define READ_VSID_FIELD(vids, sg, offset, shift, mask) \ argument
117 #define READ_VSID_FIELD_OFFESET0(vids, sg, shift, mask) \ argument
118 READ_VSID_FIELD(vids, sg, 0, shift, mask)
119 #define READ_VSID_FIELD_OFFESET1(vids, sg, shift, mask) \ argument
120 READ_VSID_FIELD(vids, sg, 1, shift, mask)
121 #define READ_VSID_FIELD_OFFESET2(vids, sg, shift, mask) \ argument
122 READ_VSID_FIELD(vids, sg, 2, shift, mask)
/rk3399_ARM-atf/drivers/brcm/
H A Diproc_gpio.c58 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in gpio_set_bit() local
63 val |= BIT(shift); in gpio_set_bit()
65 val &= ~BIT(shift); in gpio_set_bit()
73 unsigned int shift = IPROC_GPIO_SHIFT(gpio); in gpio_get_bit() local
75 return !!(mmio_read_32(base + offset) & BIT(shift)); in gpio_get_bit()
/rk3399_ARM-atf/plat/mediatek/drivers/rtc/
H A Drtc_mt6359p.c13 uint16_t mask, uint16_t shift) in RTC_Config_Interface() argument
19 pmic_reg &= ~(mask << shift); in RTC_Config_Interface()
20 pmic_reg |= (data << shift); in RTC_Config_Interface()
/rk3399_ARM-atf/plat/mediatek/drivers/spmi/
H A Dspmi_common.c97 uint8_t *buf, uint16_t mask, uint16_t shift) in spmi_ext_register_readl_field() argument
105 *buf = (rdata >> shift) & mask; in spmi_ext_register_readl_field()
111 uint8_t data, uint16_t mask, uint16_t shift) in spmi_ext_register_writel_field() argument
120 tmp &= ~(mask << shift); in spmi_ext_register_writel_field()
121 tmp |= (data << shift); in spmi_ext_register_writel_field()
/rk3399_ARM-atf/plat/mediatek/drivers/pmic_wrap/
H A Dpmic_wrap_init_v3.c178 int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift) in pwrap_read_field() argument
187 *val = (rdata >> shift) & mask; in pwrap_read_field()
192 int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift) in pwrap_write_field() argument
201 data = data & ~(mask << shift); in pwrap_write_field()
202 data |= (val << shift); in pwrap_write_field()
H A Dpmic_wrap_init_common.h17 int32_t pwrap_read_field(uint32_t reg, uint32_t *val, uint32_t mask, uint32_t shift);
19 int32_t pwrap_write_field(uint32_t reg, uint32_t val, uint32_t mask, uint32_t shift);
/rk3399_ARM-atf/plat/mediatek/include/drivers/
H A Dspmi_api.h27 uint8_t *buf, uint16_t mask, uint16_t shift);
29 uint8_t data, uint16_t mask, uint16_t shift);
/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.h13 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) argument
/rk3399_ARM-atf/plat/intel/soc/common/lib/sha/
H A Dsha.h50 static inline uint64_t ror64(uint64_t input, unsigned int shift) in ror64() argument
52 return (input >> (shift & 63)) | (input << ((-shift) & 63)); in ror64()
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.h21 #define BITS_WMSK(msk, shift) ((msk) << (shift + REG_MSK_SHIFT)) argument
/rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/
H A Dddrc.c63 uint32_t map, shift, highest; in bist() local
83 shift = (3U - i % 4U) * 8U + 2U; in bist()
84 map = (temp32 >> shift) & U(0x3F); in bist()
93 shift = (3U - pos % 4U) * 8U + 2U; in bist()
95 pos >> 2U, shift, map_save); in bist()
96 temp32 = map_save & ~(U(0x3F) << shift); in bist()
97 temp32 |= 8U << shift; in bist()
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c60 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) argument
61 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) argument
62 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift) argument
63 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift) argument
64 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift) argument
65 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift) argument

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