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Searched refs:sel (Results 1 – 16 of 16) sorted by relevance

/rk3399_ARM-atf/include/dt-bindings/clock/
H A Dstm32mp21-clksrc.h46 #define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ argument
48 (sel)))
150 #define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ argument
152 ((sel) << FLEX_SEL_SHIFT) |\
164 #define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ argument
167 (sel))
H A Dstm32mp25-clksrc.h46 #define MUX_CFG(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ argument
48 (sel)))
169 #define FLEXGEN_CFG(ch, sel, pdiv, fdiv) ((CMD_FLEXGEN << CMD_SHIFT) |\ argument
171 ((sel) << FLEX_SEL_SHIFT) |\
183 #define MCO_CFG(addr, sel, status) (CMD_ADDR_BIT |\ argument
186 (sel))
H A Dstm32mp13-clksrc.h72 #define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ argument
74 (sel)))
77 #define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\ argument
79 (sel)) | CLK_ON_MASK)
85 #define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ argument
87 (sel)) | CLK_ON_MASK)
H A Dstm32mp15-clksrc.h46 #define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ argument
48 (sel))
51 #define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ argument
53 (sel) | CLK_ON_MASK)
177 #define MCO_ON_CFG(addr, sel) (CMD_ADDR_BIT |\ argument
180 (sel))
/rk3399_ARM-atf/drivers/rpi3/gpio/
H A Drpi3_gpio.c51 uint32_t sel = mmio_read_32(reg_sel); in rpi3_gpio_get_select() local
53 ret = (sel >> shift) & 0x07; in rpi3_gpio_get_select()
76 uint32_t sel = mmio_read_32(reg_sel); in rpi3_gpio_set_select() local
79 sel = (sel & (~mask)) | ((fsel << shift) & mask); in rpi3_gpio_set_select()
80 mmio_write_32(reg_sel, sel); in rpi3_gpio_set_select()
/rk3399_ARM-atf/plat/rockchip/common/scmi/
H A Drockchip_common_clock.c59 unsigned long parent_rate, sel, div; in clk_scmi_common_get_rate() local
61 sel = mmio_read_32(clock->info[MUX_ADDR_INFO]) >> in clk_scmi_common_get_rate()
63 sel = sel & (BIT(clock->info[MUX_WIDTH_INFO]) - 1); in clk_scmi_common_get_rate()
67 parent_rate = clk_scmi_common_get_parent_rate(clock, sel); in clk_scmi_common_get_rate()
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.c193 int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) in clk_mux_set_parent() argument
203 mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask); in clk_mux_set_parent()
226 uint8_t sel; in _clk_stm32_set_parent() local
245 for (sel = 0; sel < parents->num_parents; sel++) { in _clk_stm32_set_parent()
246 if (parents->id_parents[sel] == (uint16_t)clkp) { in _clk_stm32_set_parent()
254 err = clk_mux_set_parent(priv, pid, sel); in _clk_stm32_set_parent()
289 int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel) in _clk_stm32_set_parent_by_index() argument
299 return clk_mux_set_parent(priv, pid, sel); in _clk_stm32_set_parent_by_index()
307 int sel; in _clk_stm32_get_parent() local
322 sel = ops->get_parent(priv, clk_id); in _clk_stm32_get_parent()
[all …]
H A Dstm32mp1_clk.c230 static int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) in clk_mux_set_parent() argument
239 mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask); in clk_mux_set_parent()
262 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in stm32_clk_configure_mux() local
264 return clk_mux_set_parent(priv, mux, sel); in stm32_clk_configure_mux()
484 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ member
516 .sel = (s), \
528 .sel = _UNKNOWN_SEL, \
540 .sel = (s), \
552 .sel = _UNKNOWN_SEL, \
981 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); in stm32mp1_clk_get_sel()
[all …]
H A Dclk-stm32-core.h163 int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel);
203 int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel);
H A Dclk-stm32mp2.c1258 uint32_t sel; in clk_flexgen_get_parent() local
1264 sel = mmio_read_32(rcc_base + address) & RCC_XBARxCFGR_XBARxSEL_MASK; in clk_flexgen_get_parent()
1266 return sel; in clk_flexgen_get_parent()
2386 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in stm32_clk_configure_mux() local
2388 return clk_mux_set_parent(priv, mux_id, sel); in stm32_clk_configure_mux()
H A Dclk-stm32mp13.c1171 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; in stm32_clk_configure_clk() local
1181 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); in stm32_clk_configure_clk()
1198 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; in stm32_clk_configure_mux() local
1200 return clk_mux_set_parent(priv, mux, sel); in stm32_clk_configure_mux()
/rk3399_ARM-atf/plat/allwinner/sun50i_h616/
H A Dsunxi_h616_dtb.c28 static uint32_t armv8_get_ccsidr(unsigned int sel) in armv8_get_ccsidr() argument
32 __asm__ volatile ("msr CSSELR_EL1, %0\n" :: "r" (sel)); in armv8_get_ccsidr()
/rk3399_ARM-atf/drivers/renesas/rza/cpg/
H A Dcpg.c349 static void cpg_selector_on_off(uint32_t sel, uint8_t flag) in cpg_selector_on_off() argument
355 switch (sel) { in cpg_selector_on_off()
743 uint32_t sel = cpg_xspi_table[index].selector << seldiv_pos; in cpg_set_xspi_clock() local
745 sel |= 0x10000 << seldiv_pos; in cpg_set_xspi_clock()
746 mmio_write_32(CPG_PL3_SSEL, sel); in cpg_set_xspi_clock()
765 uint8_t sel; in cpg_get_xspi_clock() local
782 sel = (uint8_t)((mmio_read_32(CPG_PL3_SSEL) >> seldiv_pos) & 1); in cpg_get_xspi_clock()
785 int frequency = cpg_rsearch_spi_clk_table(sel, div); in cpg_get_xspi_clock()
788 ERROR("CPG register value error (sel=%d, div=%d) in %s", sel, in cpg_get_xspi_clock()
/rk3399_ARM-atf/plat/mediatek/drivers/gpio/
H A Dmtgpio_common.c221 static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel) in mt_set_gpio_pull_select_chip() argument
225 if (sel == MT_GPIO_PULL_NONE) { in mt_set_gpio_pull_select_chip()
227 } else if (sel == MT_GPIO_PULL_UP) { in mt_set_gpio_pull_select_chip()
229 } else if (sel == MT_GPIO_PULL_DOWN) { in mt_set_gpio_pull_select_chip()
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/gpio/
H A Dmtgpio.c287 void mt_set_gpio_pull_select_chip(uint32_t pin, int sel) in mt_set_gpio_pull_select_chip() argument
298 if (sel == GPIO_PULL_NONE) { in mt_set_gpio_pull_select_chip()
306 } else if (sel == GPIO_PULL_UP) { in mt_set_gpio_pull_select_chip()
313 } else if (sel == GPIO_PULL_DOWN) { in mt_set_gpio_pull_select_chip()
/rk3399_ARM-atf/drivers/ufs/
H A Dufs.c527 uint8_t index, uint8_t sel, in ufs_prepare_query() argument
547 query_upiu->ts.desc.selector = sel; in ufs_prepare_query()
730 static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel, in ufs_query() argument
750 ufs_prepare_query(&utrd, op, idn, index, sel, buf, size); in ufs_query()