230 static int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel)  in clk_mux_set_parent()  argument
239 	mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask);  in clk_mux_set_parent()
262 	int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;  in stm32_clk_configure_mux()  local
264 	return clk_mux_set_parent(priv, mux, sel);  in stm32_clk_configure_mux()
484 	uint8_t sel; /* Relates to enum stm32mp1_parent_sel */  member
516 		.sel = (s),				\
528 		.sel = _UNKNOWN_SEL,			\
540 		.sel = (s),				\
552 		.sel = _UNKNOWN_SEL,			\
981 	return (enum stm32mp1_parent_sel)(gate_ref(i)->sel);  in stm32mp1_clk_get_sel()
991 	const struct stm32mp1_clk_sel *sel;  in stm32mp1_clk_get_parent()  local
1022 	sel = clk_sel_ref(s);  in stm32mp1_clk_get_parent()
1023 	p_sel = (mmio_read_32(rcc_base + sel->offset) &  in stm32mp1_clk_get_parent()
1024 		 (sel->msk << sel->src)) >> sel->src;  in stm32mp1_clk_get_parent()
1025 	if (p_sel < sel->nb_parent) {  in stm32mp1_clk_get_parent()
1026 		return (int)sel->parent[p_sel];  in stm32mp1_clk_get_parent()
2073 	uint32_t sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT;  in stm32_clk_configure_clk()  local
2083 					   (sel & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT);  in stm32_clk_configure_clk()
2373 		const struct stm32mp1_clk_sel *sel;  in stm32mp1_clk_init()  local
2375 		sel = clk_sel_ref(_USBPHY_SEL);  in stm32mp1_clk_init()
2376 		usbreg_mask = (uint32_t)sel->msk << sel->src;  in stm32mp1_clk_init()
2377 		sel = clk_sel_ref(_USBO_SEL);  in stm32mp1_clk_init()
2378 		usbreg_mask |= (uint32_t)sel->msk << sel->src;  in stm32mp1_clk_init()
2480 		const struct stm32mp1_clk_sel *sel = clk_sel_ref(s);  in get_parent_id_parent()  local
2482 		p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) &  in get_parent_id_parent()
2483 			sel->msk;  in get_parent_id_parent()
2485 		if (p_sel < sel->nb_parent) {  in get_parent_id_parent()
2486 			return (int)sel->parent[p_sel];  in get_parent_id_parent()