Home
last modified time | relevance | path

Searched refs:registers (Results 1 – 25 of 55) sorted by relevance

123

/rk3399_ARM-atf/plat/mediatek/drivers/uart/
H A Duart.c31 mmio_write_32(UART_EFR(base), uart->registers.efr); in mt_uart_restore()
32 mmio_write_32(UART_LCR(base), uart->registers.lcr); in mt_uart_restore()
33 mmio_write_32(UART_FCR(base), uart->registers.fcr); in mt_uart_restore()
36 mmio_write_32(UART_HIGHSPEED(base), uart->registers.highspeed); in mt_uart_restore()
37 mmio_write_32(UART_FRACDIV_L(base), uart->registers.fracdiv_l); in mt_uart_restore()
38 mmio_write_32(UART_FRACDIV_M(base), uart->registers.fracdiv_m); in mt_uart_restore()
40 uart->registers.lcr | UART_LCR_DLAB); in mt_uart_restore()
41 mmio_write_32(UART_DLL(base), uart->registers.dll); in mt_uart_restore()
42 mmio_write_32(UART_DLH(base), uart->registers.dlh); in mt_uart_restore()
43 mmio_write_32(UART_LCR(base), uart->registers.lcr); in mt_uart_restore()
[all …]
H A Duart.h91 struct mt_uart_register registers; member
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-8.rst5 | Title | Not saving x0 to x3 registers can leak information from one |
28 into the firmware. However, for an SMC exception, the general purpose registers
32 caller in registers ``x0`` to ``x3``. In TF-A, these return values are written
37 called. It restores the values of all general purpose registers taken from the
38 CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
45 * This function restores all general purpose registers except x30 from the
75 SMCs it would need to be aware of which return registers contain valid data, so
76 it can sanitise any unused return registers. On the other hand, mitigating this
78 information is leaked through registers ``x0`` to ``x3``, by preserving the
82 ``SP_MIN`` already saves all general purpose registers - including ``r0`` to
[all …]
H A Dsecurity-advisory-tfv-5.rst38 to the list of saved/restored registers both when entering EL3 and also
H A Dsecurity-advisory-tfv-2.rst31 by saving and restoring the appropriate debug registers), this may allow a
/rk3399_ARM-atf/docs/components/
H A Dcontext-management-library.rst13 The general-purpose registers, most of the system registers and vector registers
34 configuration of system registers independent of other security states to access
39 (EL2/EL1, vector, general-purpose registers), will be overwritten, as the software
80 EL3 should initialise and monitor S-EL2 registers only. S-EL1 registers should
82 absent, S-EL1 registers should be initialised from EL3.
167 during cold and warmboot and el3 registers initialisation in assembly code.
237 When FEAT_IDTE3 is enabled, the ID registers ID_AA64DFR0_EL1 and
241 corresponding registers from lower exception levels. Because debug and
242 trace features can vary across CPUs, these ID registers are cached
246 The per-cpu cached ID registers are initialized in ``psci_arch_setup()``
[all …]
H A Darm-sip-service.rst66 switched, the parameters *Cookie hi* and *Cookie lo* are passed in CPU registers
73 entered for the first time, following power on. This means CPU registers that
75 registers should not be expected to hold their values before the call was made.
88 Instead, execution starts at the supplied entry point, with the CPU registers 0
H A Dfirme.rst74 feature registers.
75 - The granule management service publishes two feature registers:
H A Drmm-el3-comms-spec.rst1057 and restore the following registers during a world switch.
1061 * General-purpose registers: ``x0–x30``
1068 EL3 shall save and restore all EL2 system registers corresponding to
1069 features enabled by EL3 (that is, registers with the ``_EL2``
1070 architectural suffix), excluding the registers listed below (see
1076 key registers:
1089 EL3 shall not save or restore the registers listed below. If the Realm
1090 world makes use of any of the registers below, the Realm Management
1095 * EL2 physical timer registers
1096 * EL2 virtual timer registers
[all …]
H A Dsdei.rst33 registers a handler for that event [3], enables the event [5], and unmasks all
233 As part of initialisation, the SDEI client registers a handler for a platform
310 registers except ``x0`` to ``x17``. This has significance if event handler is
332 return to the handler, the epilogue never gets executed, and registers ``x29``
/rk3399_ARM-atf/tools/marvell/doimage/secure/
H A Dsec_img_8K.cfg26 # SecureBootControl and EfuseBurnControl registers array
H A Dsec_img_7K.cfg26 # SecureBootControl and EfuseBurnControl registers array
/rk3399_ARM-atf/services/std_svc/spm/el3_spmc/
H A Dspmc_main.c1627 uint32_t *registers = (uint32_t *)chars; in spmc_ffa_console_log() local
1628 registers[0] = (uint32_t)x2; in spmc_ffa_console_log()
1629 registers[1] = (uint32_t)x3; in spmc_ffa_console_log()
1630 registers[2] = (uint32_t)x4; in spmc_ffa_console_log()
1631 registers[3] = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); in spmc_ffa_console_log()
1632 registers[4] = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X6); in spmc_ffa_console_log()
1633 registers[5] = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X7); in spmc_ffa_console_log()
1636 uint64_t *registers = (uint64_t *)chars; in spmc_ffa_console_log() local
1637 registers[0] = x2; in spmc_ffa_console_log()
1638 registers[1] = x3; in spmc_ffa_console_log()
[all …]
/rk3399_ARM-atf/docs/plat/marvell/armada/misc/
H A Dmvebu-io-win.rst15 - **0x3** = PCIe registers
/rk3399_ARM-atf/docs/perf/
H A Dperformance-monitoring-unit.rst50 ``PMCR`` registers. These can be accessed at all privilege levels.
147 regardless of how the other PMU system registers or bit fields are
H A Dpsci-performance-instr.rst20 The PMU is a generalized abstraction for accessing CPU hardware registers used to
27 instance, the PSCI Statistics service registers the PMF service
/rk3399_ARM-atf/docs/design/
H A Dtrusted-board-boot-build.rst49 root-key storage registers present in the platform. On Juno, these
50 registers are read-only. On FVP Base and Cortex models, the registers
/rk3399_ARM-atf/docs/getting_started/
H A Dbuild-options.rst191 the AArch32 system registers to be included when saving and restoring the
197 registers to be included when saving and restoring the CPU context. Default
202 registers to be included when saving and restoring the CPU context.
206 registers to be saved/restored when entering/exiting an EL2 execution
211 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
222 SVE registers to be included when saving and restoring the CPU context. Note
384 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers
392 restrict overwriting certain EL3 registers after boot.
394 system registers that are not expected to be overwritten after boot.
400 This feature currently traps access to all EL3 registers in
[all …]
/rk3399_ARM-atf/docs/plat/arm/
H A Darm-build-options.rst14 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
32 - ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to
34 to have a Linux kernel image as BL33 by preparing the registers to these
71 registers.
/rk3399_ARM-atf/fdts/
H A Dstmm_template.dts28 * System registers, rtc, uart and etc regions for access from S-EL0.
/rk3399_ARM-atf/docs/plat/arm/arm_fpga/
H A Dindex.rst30 - ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers.
34 code (only architectural system registers, and no errata).
/rk3399_ARM-atf/docs/plat/arm/morello/
H A Dindex.rst15 The SCP initializes the RVBAR registers to point to the AP_BL1. Once RVBAR is
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/fdts/
H A Drdn2_stmm_sel0_manifest.dts48 * System registers region for access from S-EL0.
/rk3399_ARM-atf/docs/plat/nxp/
H A Dnxp-ls-fuse-prov.rst20 - SFP registers to be written to:
92 - At U-Boot prompt, verify that SNVS registers for OTPMK are correctly written:
/rk3399_ARM-atf/plat/renesas/common/
H A Dcommon.mk80 PLAT_INCLUDES := -Iplat/renesas/common/include/registers \

123