docs/getting_started/build-options.rst

185    the AArch32 system registers to be included when saving and restoring the
191    registers to be included when saving and restoring the CPU context. Default
196    registers to be included when saving and restoring the CPU context.
200    registers to be saved/restored when entering/exiting an EL2 execution
205    Authentication for Secure world. This will cause the ARMv8.3-PAuth registers
216    SVE registers to be included when saving and restoring the CPU context. Note
360    (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers
368    restrict overwriting certain EL3 registers after boot.
370    system registers that are not expected to be overwritten after boot.
376       This feature currently traps access to all EL3 registers in
400       ID registers to EL3. This can incur a performance impact and platforms
406    require any settings from EL3 as the controls are present in EL2 registers
409    EL3 should configure the EL2 registers. This flag
477    at EL2 and below, and context switch relevant registers.  This flag
482    at EL2 and below, and context switch relevant registers.  This flag
487    at EL2 and below, and context switch relevant registers.  This flag
492    at EL2 and below, and context switch relevant registers.  This flag
498    registers to the EL2 context save/restore operations. This flag can take
510    registers and context switch them.
517    SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and
525    128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1,
555    access their own MPAM registers without trapping into EL3. This option
573    registers from non-secure world. This flag can take the values 0 to 2, to
578    registers from non-secure world. This flag can take the values 0 to 2, to
625    world data in the Z-registers which are aliased by the SIMD and FP registers.
889    this to 1 if it wants the timer registers to be saved and restored. This
924    registers when the cluster goes through a power cycle. This is disabled by
1177    The DSU driver allows save/restore of DSU PMU registers through
1178    ``PRESERVE_DSU_PMU_REGS`` build option, provides access to PMU registers at
1303   bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
1316   buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an
1322   control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented
1338   registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented
1343 - ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers
1527    registers so are enabled together. Using this option without