Lines Matching refs:registers

13 The general-purpose registers, most of the system registers and vector registers
34 configuration of system registers independent of other security states to access
39 (EL2/EL1, vector, general-purpose registers), will be overwritten, as the software
80 EL3 should initialise and monitor S-EL2 registers only. S-EL1 registers should
82 absent, S-EL1 registers should be initialised from EL3.
167    during cold and warmboot and el3 registers initialisation in assembly code.
237 When FEAT_IDTE3 is enabled, the ID registers ID_AA64DFR0_EL1 and
241 corresponding registers from lower exception levels. Because debug and
242 trace features can vary across CPUs, these ID registers are cached
246 The per-cpu cached ID registers are initialized in ``psci_arch_setup()``
371 process, the SPMD duly registers its handlers with the PSCI library.
419 This function initializes all EL3 registers whose values do not change during the
433 at EL3 to facilitate the saving and restoration of the EL1 system registers
443 at EL3 to facilitate the saving and restoration of the EL2 system registers
451 save and restore the Pauth registers during world switch.
454 general purpose and Pauth registers while we enter EL3 from lower ELs via
485   registers that are never context switched. The values they write must never
490   in any EL2 registers that are necessary for execution in EL1 with no EL2 present.
505 of the EL3 system registers whose values are identical across all the CPUs
507 The Per-world context structure is intended for managing EL3 system registers with
510 structure and is intended to manage specific EL3 registers.
524 that caches architectural ID registers common across all CPUs in a world.
540 Previously, while the CPU is in execution at EL3, the system registers persist
542 EL3 from NS world, the EL1 and EL2 system registers which might be modified in
544 Further the EL3 registers also hold on to the values configured for Non-secure
552 registers configured for lower exception levels.