| /rk3399_ARM-atf/include/lib/el3_runtime/ |
| H A D | context_el2.h | 231 #define read_el2_ctx_common(ctx, reg) (((ctx)->common).reg) argument
233 #define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ argument
236 #define write_el2_ctx_common_sysreg128(ctx, reg, val) ((((ctx)->common).reg) \ argument
240 #define read_el2_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) argument
241 #define write_el2_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ argument
244 #define read_el2_ctx_mte2(ctx, reg) ULL(0) argument
245 #define write_el2_ctx_mte2(ctx, reg, val) argument
249 #define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg) argument
250 #define write_el2_ctx_fgt(ctx, reg, val) ((((ctx)->fgt).reg) \ argument
253 #define read_el2_ctx_fgt(ctx, reg) ULL(0) argument
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| H A D | context_el1.h | 191 #define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg) argument
193 #define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ argument
196 #define write_el1_ctx_common_sysreg128(ctx, reg, val) ((((ctx)->common).reg) \ argument
199 #define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg) argument
200 #define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \ argument
204 #define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg) argument
205 #define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \ argument
208 #define read_el1_ctx_aarch32(ctx, reg) ULL(0) argument
209 #define write_el1_ctx_aarch32(ctx, reg, val) argument
213 #define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) argument
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| /rk3399_ARM-atf/drivers/renesas/rcar/pfc/ |
| H A D | pfc_init.c | 40 #define PRR_PRODUCT_ERR(reg) \ argument
43 reg); \
47 #define PRR_CUT_ERR(reg) \ argument
50 reg); \
56 uint32_t reg; in rcar_pfc_init() local
58 reg = mmio_read_32(RCAR_PRR); in rcar_pfc_init()
60 switch (reg & PRR_PRODUCT_MASK) { in rcar_pfc_init()
62 switch (reg & PRR_CUT_MASK) { in rcar_pfc_init()
84 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
89 switch (reg & PRR_PRODUCT_MASK) { in rcar_pfc_init()
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| /rk3399_ARM-atf/drivers/renesas/rcar/qos/ |
| H A D | qos_init.c | 61 #define PRR_PRODUCT_ERR(reg) \ argument
64 "initialize not supported.\n", reg); \
68 #define PRR_CUT_ERR(reg) \ argument
71 "initialize not supported.\n", reg); \
77 uint32_t reg; in rcar_qos_init() local
90 reg = mmio_read_32(PRR); in rcar_qos_init()
92 switch (reg & PRR_PRODUCT_MASK) { in rcar_qos_init()
95 switch (reg & PRR_CUT_MASK) { in rcar_qos_init()
111 switch (reg & PRR_CUT_MASK) { in rcar_qos_init()
118 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
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| /rk3399_ARM-atf/drivers/renesas/rzg/pfc/ |
| H A D | pfc_init.c | 31 #define PRR_PRODUCT_ERR(reg) \ argument
34 reg); \
38 #define PRR_CUT_ERR(reg) \ argument
41 reg); \
47 uint32_t reg; in rzg_pfc_init() local
49 reg = mmio_read_32(RCAR_PRR); in rzg_pfc_init()
51 switch (reg & PRR_PRODUCT_MASK) { in rzg_pfc_init()
65 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
70 switch (reg & PRR_PRODUCT_MASK) { in rzg_pfc_init()
73 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
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| /rk3399_ARM-atf/drivers/renesas/rzg/qos/ |
| H A D | qos_init.c | 45 #define PRR_PRODUCT_ERR(reg) \ argument
48 "initialize not supported.\n", reg); \
52 #define PRR_CUT_ERR(reg) \ argument
55 "initialize not supported.\n", reg); \
61 uint32_t reg; in rzg_qos_init() local
74 reg = mmio_read_32(PRR); in rzg_qos_init()
76 switch (reg & PRR_PRODUCT_MASK) { in rzg_qos_init()
79 switch (reg & PRR_CUT_MASK) { in rzg_qos_init()
92 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
97 switch (reg & PRR_CUT_MASK) { in rzg_qos_init()
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| /rk3399_ARM-atf/lib/extensions/sme/ |
| H A D | sme.c | 19 u_register_t reg; in sme_enable() local
26 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_enable()
27 reg |= SCR_ENTP2_BIT; in sme_enable()
28 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_enable()
33 u_register_t reg; in sme_enable_per_world() local
36 reg = per_world_ctx->ctx_cptr_el3; in sme_enable_per_world()
37 reg |= ESM_BIT; in sme_enable_per_world()
38 per_world_ctx->ctx_cptr_el3 = reg; in sme_enable_per_world()
80 u_register_t reg; in sme_disable() local
87 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_disable()
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| /rk3399_ARM-atf/plat/mediatek/drivers/mtcmos/ |
| H A D | mtcmos.c | 35 static int mtcmos_wait_for_state(uint32_t reg, uint32_t mask, bool is_set) in mtcmos_wait_for_state() argument
41 if ((mmio_read_32(reg) & mask) == expect) in mtcmos_wait_for_state()
48 __func__, reg, mask, is_set, mmio_read_32(reg)); in mtcmos_wait_for_state()
69 static int spm_mtcmos_ctrl(enum mtcmos_state state, uintptr_t reg, in spm_mtcmos_ctrl() argument
85 mmio_setbits_32(reg, SRAM_PDN); in spm_mtcmos_ctrl()
86 ret = mtcmos_wait_for_state(reg, SRAM_PDN_ACK, true); in spm_mtcmos_ctrl()
91 mmio_setbits_32(reg, RTFF_CLK_DIS); in spm_mtcmos_ctrl()
92 mmio_setbits_32(reg, RTFF_SAVE); in spm_mtcmos_ctrl()
93 mmio_clrbits_32(reg, RTFF_SAVE); in spm_mtcmos_ctrl()
94 mmio_clrbits_32(reg, RTFF_CLK_DIS); in spm_mtcmos_ctrl()
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| /rk3399_ARM-atf/include/services/ |
| H A D | drtm_svc.h | 118 #define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \ argument
120 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \
126 #define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \ argument
128 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK \
134 #define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \ argument
136 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK \
142 #define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \ argument
144 reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK \
150 #define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \ argument
152 reg = (((reg) & \
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| /rk3399_ARM-atf/drivers/cadence/nand/ |
| H A D | cdns_nand.c | 34 uint32_t reg = 0U; in cdns_nand_wait_idle() local
38 reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS)); in cdns_nand_wait_idle()
39 } while (CNF_GET_CTRL_BUSY(reg) != 0U); in cdns_nand_wait_idle()
45 uint32_t reg = 0U; in cdns_nand_wait_thread_ready() local
49 reg = mmio_read_32(CNF_CMDREG(TRD_STATUS)); in cdns_nand_wait_thread_ready()
50 reg &= (1U << (uint32_t)thread_id); in cdns_nand_wait_thread_ready()
51 } while (reg != 0U); in cdns_nand_wait_thread_ready()
71 uint32_t reg = 0U; in cdns_nand_last_opr_status() local
74 reg = mmio_read_32(CNF_CTRLPARAM(FEATURE)); in cdns_nand_last_opr_status()
75 nthreads = CNF_GET_NTHREADS(reg); in cdns_nand_last_opr_status()
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| /rk3399_ARM-atf/drivers/marvell/secure_dfx_access/ |
| H A D | armada_thermal.c | 64 uint32_t reg; in armada_ap806_thermal_read() local
66 reg = mmio_read_32(TSEN_STATUS); in armada_ap806_thermal_read()
68 reg = ((reg & TSEN_STATUS_TEMP_OUT_MASK) >> in armada_ap806_thermal_read()
76 if (reg >= THERMAL_SEN_OUTPUT_MSB) in armada_ap806_thermal_read()
77 reg -= THERMAL_SEN_OUTPUT_COMP; in armada_ap806_thermal_read()
79 *temp = ((COEF_M * ((signed int)reg)) - COEF_B); in armada_ap806_thermal_read()
90 uint32_t reg; in armada_ap806_thermal_overheat_irq_init() local
93 reg = mmio_read_32(DFX_IRQ_CAUSE_REG); in armada_ap806_thermal_overheat_irq_init()
96 reg = mmio_read_32(DFX_IRQ_MASK_REG); in armada_ap806_thermal_overheat_irq_init()
97 reg |= DFX_IRQ_TSEN_OVERHEAT_OFFSET; in armada_ap806_thermal_overheat_irq_init()
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| /rk3399_ARM-atf/plat/imx/common/sci/ |
| H A D | imx8_mu.c | 13 uint32_t reg, i; in MU_Resume() local
15 reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_Resume()
17 reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 in MU_Resume()
19 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_Resume()
28 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableRxFullInt() local
30 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); in MU_EnableRxFullInt()
31 reg |= MU_CR_RIE0_MASK1 >> index; in MU_EnableRxFullInt()
32 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableRxFullInt()
37 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableGeneralInt() local
39 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); in MU_EnableGeneralInt()
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| /rk3399_ARM-atf/plat/marvell/armada/a8k/common/ |
| H A D | plat_thermal.c | 45 uint32_t reg, timeout = 0; in ext_tsen_probe() local
57 reg = mmio_read_32((uintptr_t)&base->ext_tsen_ctrl_lsb); in ext_tsen_probe()
58 reg &= ~THERMAL_SEN_CTRL_LSB_RST_OFFSET; /* de-assert TSEN_RESET */ in ext_tsen_probe()
59 reg |= THERMAL_SEN_CTRL_LSB_EN_MASK; /* set TSEN_EN to 1 */ in ext_tsen_probe()
60 reg |= THERMAL_SEN_CTRL_LSB_STRT_MASK; /* set TSEN_START to 1 */ in ext_tsen_probe()
61 mmio_write_32((uintptr_t)&base->ext_tsen_ctrl_lsb, reg); in ext_tsen_probe()
63 reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); in ext_tsen_probe()
64 while ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0 && in ext_tsen_probe()
67 reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); in ext_tsen_probe()
71 if ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0) { in ext_tsen_probe()
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| /rk3399_ARM-atf/drivers/allwinner/axp/ |
| H A D | common.c | 32 int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) in axp_clrsetbits() argument
37 ret = axp_read(reg); in axp_clrsetbits()
43 return axp_write(reg, val); in axp_clrsetbits()
79 const struct axp_regulator *reg) in setup_regulator() argument
85 if (mvolt < reg->min_volt || mvolt > reg->max_volt) in setup_regulator()
88 val = (mvolt / reg->step) - (reg->min_volt / reg->step); in setup_regulator()
89 if (val > reg->split) in setup_regulator()
90 val = ((val - reg->split) / 2) + reg->split; in setup_regulator()
92 axp_write(reg->volt_reg, val); in setup_regulator()
93 axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); in setup_regulator()
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| /rk3399_ARM-atf/plat/mediatek/drivers/pmic/ |
| H A D | pmic_psc.c | 23 const struct pmic_psc_reg *reg; in read_pmic_psc_reg() local
28 reg = &pmic_psc->regs[reg_name]; in read_pmic_psc_reg()
29 pmic_psc->read_field(reg->reg_addr, &val, reg->reg_mask, reg->reg_shift); in read_pmic_psc_reg()
35 const struct pmic_psc_reg *reg; in set_pmic_psc_reg() local
40 reg = &pmic_psc->regs[reg_name]; in set_pmic_psc_reg()
41 pmic_psc->write_field(reg->reg_addr, 1, reg->reg_mask, reg->reg_shift); in set_pmic_psc_reg()
47 const struct pmic_psc_reg *reg; in clr_pmic_psc_reg() local
52 reg = &pmic_psc->regs[reg_name]; in clr_pmic_psc_reg()
53 pmic_psc->write_field(reg->reg_addr, 0, reg->reg_mask, reg->reg_shift); in clr_pmic_psc_reg()
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| /rk3399_ARM-atf/drivers/allwinner/ |
| H A D | sunxi_rsb.c | 39 uint32_t reg, tries = MAX_TRIES; in rsb_wait_bit() local
42 reg = mmio_read_32(SUNXI_R_RSB_BASE + offset); in rsb_wait_bit()
43 while ((reg & mask) && --tries); /* transaction in progress */ in rsb_wait_bit()
44 if (reg & mask) { in rsb_wait_bit()
54 uint32_t reg; in rsb_wait_stat() local
60 reg = mmio_read_32(SUNXI_R_RSB_BASE + RSB_STAT); in rsb_wait_stat()
61 if (reg == 0x01) in rsb_wait_stat()
64 ERROR("%s: 0x%x\n", desc, reg); in rsb_wait_stat()
65 return -reg; in rsb_wait_stat()
113 uint32_t reg; in rsb_set_bus_speed() local
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| /rk3399_ARM-atf/drivers/renesas/rcar/cpld/ |
| H A D | ulcb_cpld.c | 36 uint32_t reg; in gpio_set_value() local
38 reg = mmio_read_32(addr); in gpio_set_value()
40 reg |= (1 << gpio); in gpio_set_value()
42 reg &= ~(1 << gpio); in gpio_set_value()
43 mmio_write_32(addr, reg); in gpio_set_value()
48 uint32_t reg; in gpio_direction_output() local
50 reg = mmio_read_32(addr); in gpio_direction_output()
51 reg |= (1 << gpio); in gpio_direction_output()
52 mmio_write_32(addr, reg); in gpio_direction_output()
57 uint32_t reg; in gpio_pfc() local
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | asm_macros.S | 77 .macro dcache_line_size reg, tmp
80 mov \reg, #4
81 lsl \reg, \reg, \tmp
85 .macro icache_line_size reg, tmp
88 mov \reg, #4
89 lsl \reg, \reg, \tmp
231 .macro read reg:req
235 mrs x0, \reg
242 .macro write reg:req
246 msr \reg, x1
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| /rk3399_ARM-atf/lib/extensions/sve/ |
| H A D | sve.c | 43 u_register_t reg; in sve_init_el2_unused() local
52 reg = read_cptr_el2(); in sve_init_el2_unused()
53 reg &= ~(CPTR_EL2_TZ_BIT); in sve_init_el2_unused()
54 reg |= ULL(3) << CPTR_EL2_ZEN_SHIFT; in sve_init_el2_unused()
55 write_cptr_el2(reg); in sve_init_el2_unused()
60 u_register_t reg; in sve_disable_per_world() local
63 reg = per_world_ctx->ctx_cptr_el3; in sve_disable_per_world()
64 reg &= ~CPTR_EZ_BIT; /* Trap SVE */ in sve_disable_per_world()
65 per_world_ctx->ctx_cptr_el3 = reg; in sve_disable_per_world()
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| /rk3399_ARM-atf/lib/extensions/tcr/ |
| H A D | tcr2.c | 14 u_register_t reg; in tcr2_enable() local
23 reg = read_ctx_reg(state, CTX_SCR_EL3); in tcr2_enable()
24 reg |= SCR_TCR2EN_BIT; in tcr2_enable()
25 write_ctx_reg(state, CTX_SCR_EL3, reg); in tcr2_enable()
30 u_register_t reg; in tcr2_disable() local
39 reg = read_ctx_reg(state, CTX_SCR_EL3); in tcr2_disable()
40 reg &= ~SCR_TCR2EN_BIT; in tcr2_disable()
41 write_ctx_reg(state, CTX_SCR_EL3, reg); in tcr2_disable()
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hisi_pwrc.c | 42 unsigned int reg = 0; in hisi_pwrc_set_cluster_wfi() local
45 reg = mmio_read_32(ACPU_SC_SNOOP_PWD); in hisi_pwrc_set_cluster_wfi()
46 reg |= PD_DETECT_START0; in hisi_pwrc_set_cluster_wfi()
47 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); in hisi_pwrc_set_cluster_wfi()
49 reg = mmio_read_32(ACPU_SC_SNOOP_PWD); in hisi_pwrc_set_cluster_wfi()
50 reg |= PD_DETECT_START1; in hisi_pwrc_set_cluster_wfi()
51 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); in hisi_pwrc_set_cluster_wfi()
72 unsigned int reg, sec_entrypoint; in hisi_pwrc_setup() local
93 reg = mmio_read_32(AO_SC_SYS_CTRL1); in hisi_pwrc_setup()
95 reg |= AO_SC_SYS_CTRL1_REMAP_SRAM_AARM | in hisi_pwrc_setup()
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mq/ |
| H A D | gpc.c | 58 uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4; in gpc_save_imr_lpm() local
62 gpc_saved_imrs[core_id + imr_idx * 4] = mmio_read_32(reg); in gpc_save_imr_lpm()
63 mmio_write_32(reg, ~gpc_wake_irqs[imr_idx]); in gpc_save_imr_lpm()
70 uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4; in gpc_restore_imr_lpm() local
75 mmio_write_32(reg, val); in gpc_restore_imr_lpm()
110 uintptr_t reg; in imx_gpc_hwirq_mask() local
118 reg = gpc_imr_offset[0] + (hwirq / 32) * 4; in imx_gpc_hwirq_mask()
119 val = mmio_read_32(reg); in imx_gpc_hwirq_mask()
121 mmio_write_32(reg, val); in imx_gpc_hwirq_mask()
127 uintptr_t reg; in imx_gpc_hwirq_unmask() local
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/otp/ |
| H A D | otp.c | 35 uint32_t reg = 0; in enable_otp_clk() local
39 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
40 if (reg & CLK_NS_OTP_USER_EN) in enable_otp_clk()
46 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
47 if (reg & CLK_NS_OTP_SBPI_EN) in enable_otp_clk()
53 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
54 if (reg & PCLK_NS_OTP_EN) in enable_otp_clk()
60 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(34)); in enable_otp_clk()
61 if (reg & PCLK_PHY_OTP_EN) in enable_otp_clk()
67 reg = mmio_read_32(SCRU_BASE + SCRU_GATE_CON01); in enable_otp_clk()
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| /rk3399_ARM-atf/fdts/ |
| H A D | stm32mp251.dtsi | 22 reg = <0>;
64 reg = <0x0 0x4ac10000 0x0 0x1000>,
89 reg = <0x42080000 0x1000>;
95 reg = <0x400e0000 0x400>;
103 reg = <0x400f0000 0x400>;
111 reg = <0x40100000 0x400>;
119 reg = <0x40110000 0x400>;
127 reg = <0x40120000 0x400>;
135 reg = <0x40130000 0x400>;
143 reg = <0x40140000 0x400>;
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| /rk3399_ARM-atf/drivers/marvell/mochi/ |
| H A D | apn806_setup.c | 129 uint32_t reg; in setup_smmu() local
132 reg = mmio_read_32(SMMU_sACR); in setup_smmu()
133 reg |= SMMU_sACR_PG_64K; in setup_smmu()
134 mmio_write_32(SMMU_sACR, reg); in setup_smmu()
139 uint32_t reg; in init_aurora2() local
142 reg = mmio_read_32(CCU_GSPMU_CR); in init_aurora2()
143 reg |= GSPMU_CPU_CONTROL; in init_aurora2()
144 mmio_write_32(CCU_GSPMU_CR, reg); in init_aurora2()
154 reg = mmio_read_32(CCU_HTC_CR); in init_aurora2()
155 reg |= (0x1 << CCU_SET_POC_OFFSET); in init_aurora2()
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