1 /* 2 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL2_H 8 #define CONTEXT_EL2_H 9 10 #include <lib/extensions/sysreg128.h> 11 12 #ifndef __ASSEMBLER__ 13 14 /******************************************************************************* 15 * EL2 Registers: 16 * AArch64 EL2 system register context structure for preserving the 17 * architectural state during world switches. 18 ******************************************************************************/ 19 typedef struct el2_common_regs { 20 uint64_t actlr_el2; 21 uint64_t afsr0_el2; 22 uint64_t afsr1_el2; 23 uint64_t amair_el2; 24 uint64_t cnthctl_el2; 25 uint64_t cntvoff_el2; 26 uint64_t cptr_el2; 27 uint64_t dbgvcr32_el2; 28 uint64_t elr_el2; 29 uint64_t esr_el2; 30 uint64_t far_el2; 31 uint64_t hacr_el2; 32 uint64_t hcr_el2; 33 uint64_t hpfar_el2; 34 uint64_t hstr_el2; 35 uint64_t icc_sre_el2; 36 uint64_t ich_hcr_el2; 37 uint64_t ich_vmcr_el2; 38 uint64_t mair_el2; 39 uint64_t mdcr_el2; 40 uint64_t pmscr_el2; 41 uint64_t sctlr_el2; 42 uint64_t spsr_el2; 43 uint64_t sp_el2; 44 uint64_t tcr_el2; 45 uint64_t tpidr_el2; 46 uint64_t vbar_el2; 47 uint64_t vmpidr_el2; 48 uint64_t vpidr_el2; 49 uint64_t vtcr_el2; 50 sysreg_t vttbr_el2; 51 sysreg_t ttbr0_el2; 52 } el2_common_regs_t; 53 54 typedef struct el2_mte2_regs { 55 uint64_t tfsr_el2; 56 } el2_mte2_regs_t; 57 58 typedef struct el2_fgt_regs { 59 uint64_t hdfgrtr_el2; 60 uint64_t hafgrtr_el2; 61 uint64_t hdfgwtr_el2; 62 uint64_t hfgitr_el2; 63 uint64_t hfgrtr_el2; 64 uint64_t hfgwtr_el2; 65 } el2_fgt_regs_t; 66 67 typedef struct el2_fgt2_regs { 68 uint64_t hdfgrtr2_el2; 69 uint64_t hdfgwtr2_el2; 70 uint64_t hfgitr2_el2; 71 uint64_t hfgrtr2_el2; 72 uint64_t hfgwtr2_el2; 73 } el2_fgt2_regs_t; 74 75 typedef struct el2_ecv_regs { 76 uint64_t cntpoff_el2; 77 } el2_ecv_regs_t; 78 79 typedef struct el2_vhe_regs { 80 uint64_t contextidr_el2; 81 sysreg_t ttbr1_el2; 82 } el2_vhe_regs_t; 83 84 typedef struct el2_ras_regs { 85 uint64_t vdisr_el2; 86 uint64_t vsesr_el2; 87 } el2_ras_regs_t; 88 89 typedef struct el2_neve_regs { 90 uint64_t vncr_el2; 91 } el2_neve_regs_t; 92 93 typedef struct el2_trf_regs { 94 uint64_t trfcr_el2; 95 } el2_trf_regs_t; 96 97 typedef struct el2_csv2_regs { 98 uint64_t scxtnum_el2; 99 } el2_csv2_regs_t; 100 101 typedef struct el2_hcx_regs { 102 uint64_t hcrx_el2; 103 } el2_hcx_regs_t; 104 105 typedef struct el2_tcr2_regs { 106 uint64_t tcr2_el2; 107 } el2_tcr2_regs_t; 108 109 typedef struct el2_sxpoe_regs { 110 uint64_t por_el2; 111 } el2_sxpoe_regs_t; 112 113 typedef struct el2_sxpie_regs { 114 uint64_t pire0_el2; 115 uint64_t pir_el2; 116 } el2_sxpie_regs_t; 117 118 typedef struct el2_s2pie_regs { 119 uint64_t s2pir_el2; 120 } el2_s2pie_regs_t; 121 122 typedef struct el2_gcs_regs { 123 uint64_t gcscr_el2; 124 uint64_t gcspr_el2; 125 } el2_gcs_regs_t; 126 127 typedef struct el2_mpam_regs { 128 uint64_t mpam2_el2; 129 uint64_t mpamhcr_el2; 130 uint64_t mpamvpm0_el2; 131 uint64_t mpamvpm1_el2; 132 uint64_t mpamvpm2_el2; 133 uint64_t mpamvpm3_el2; 134 uint64_t mpamvpm4_el2; 135 uint64_t mpamvpm5_el2; 136 uint64_t mpamvpm6_el2; 137 uint64_t mpamvpm7_el2; 138 uint64_t mpamvpmv_el2; 139 } el2_mpam_regs_t; 140 141 typedef struct el2_sctlr2_regs { 142 uint64_t sctlr2_el2; 143 } el2_sctlr2_regs_t; 144 145 typedef struct el2_brbe_regs { 146 uint64_t brbcr_el2; 147 } el2_brbe_regs_t; 148 149 typedef struct el2_sysregs { 150 151 el2_common_regs_t common; 152 153 #if ENABLE_FEAT_MTE2 154 el2_mte2_regs_t mte2; 155 #endif 156 157 #if ENABLE_FEAT_FGT 158 el2_fgt_regs_t fgt; 159 #endif 160 161 #if ENABLE_FEAT_FGT2 162 el2_fgt2_regs_t fgt2; 163 #endif 164 165 #if ENABLE_FEAT_ECV 166 el2_ecv_regs_t ecv; 167 #endif 168 169 #if ENABLE_FEAT_VHE 170 el2_vhe_regs_t vhe; 171 #endif 172 173 #if ENABLE_FEAT_RAS 174 el2_ras_regs_t ras; 175 #endif 176 177 #if CTX_INCLUDE_NEVE_REGS 178 el2_neve_regs_t neve; 179 #endif 180 181 #if ENABLE_TRF_FOR_NS 182 el2_trf_regs_t trf; 183 #endif 184 185 #if ENABLE_FEAT_CSV2_2 186 el2_csv2_regs_t csv2; 187 #endif 188 189 #if ENABLE_FEAT_HCX 190 el2_hcx_regs_t hcx; 191 #endif 192 193 #if ENABLE_FEAT_TCR2 194 el2_tcr2_regs_t tcr2; 195 #endif 196 197 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 198 el2_sxpoe_regs_t sxpoe; 199 #endif 200 201 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 202 el2_sxpie_regs_t sxpie; 203 #endif 204 205 #if ENABLE_FEAT_S2PIE 206 el2_s2pie_regs_t s2pie; 207 #endif 208 209 #if ENABLE_FEAT_GCS 210 el2_gcs_regs_t gcs; 211 #endif 212 213 #if CTX_INCLUDE_MPAM_REGS 214 el2_mpam_regs_t mpam; 215 #endif 216 217 #if ENABLE_FEAT_SCTLR2 218 el2_sctlr2_regs_t sctlr2; 219 #endif 220 221 #if ENABLE_BRBE_FOR_NS 222 el2_brbe_regs_t brbe; 223 #endif 224 225 } el2_sysregs_t; 226 227 /* 228 * Macros to access members related to individual features of the el2_sysregs_t 229 * structures. 230 */ 231 #define read_el2_ctx_common(ctx, reg) (((ctx)->common).reg) 232 233 #define write_el2_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 234 = (uint64_t) (val)) 235 236 #define write_el2_ctx_common_sysreg128(ctx, reg, val) ((((ctx)->common).reg) \ 237 = (sysreg_t) (val)) 238 239 #if ENABLE_FEAT_MTE2 240 #define read_el2_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 241 #define write_el2_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 242 = (uint64_t) (val)) 243 #else 244 #define read_el2_ctx_mte2(ctx, reg) ULL(0) 245 #define write_el2_ctx_mte2(ctx, reg, val) 246 #endif /* ENABLE_FEAT_MTE2 */ 247 248 #if ENABLE_FEAT_FGT 249 #define read_el2_ctx_fgt(ctx, reg) (((ctx)->fgt).reg) 250 #define write_el2_ctx_fgt(ctx, reg, val) ((((ctx)->fgt).reg) \ 251 = (uint64_t) (val)) 252 #else 253 #define read_el2_ctx_fgt(ctx, reg) ULL(0) 254 #define write_el2_ctx_fgt(ctx, reg, val) 255 #endif /* ENABLE_FEAT_FGT */ 256 257 #if ENABLE_FEAT_FGT2 258 #define read_el2_ctx_fgt2(ctx, reg) (((ctx)->fgt2).reg) 259 #define write_el2_ctx_fgt2(ctx, reg, val) ((((ctx)->fgt2).reg) \ 260 = (uint64_t) (val)) 261 #else 262 #define read_el2_ctx_fgt2(ctx, reg) ULL(0) 263 #define write_el2_ctx_fgt2(ctx, reg, val) 264 #endif /* ENABLE_FEAT_FGT */ 265 266 #if ENABLE_FEAT_ECV 267 #define read_el2_ctx_ecv(ctx, reg) (((ctx)->ecv).reg) 268 #define write_el2_ctx_ecv(ctx, reg, val) ((((ctx)->ecv).reg) \ 269 = (uint64_t) (val)) 270 #else 271 #define read_el2_ctx_ecv(ctx, reg) ULL(0) 272 #define write_el2_ctx_ecv(ctx, reg, val) 273 #endif /* ENABLE_FEAT_ECV */ 274 275 #if ENABLE_FEAT_VHE 276 #define read_el2_ctx_vhe(ctx, reg) (((ctx)->vhe).reg) 277 #define write_el2_ctx_vhe(ctx, reg, val) ((((ctx)->vhe).reg) \ 278 = (uint64_t) (val)) 279 #define write_el2_ctx_vhe_sysreg128(ctx, reg, val) ((((ctx)->vhe).reg) \ 280 = (sysreg_t) (val)) 281 #else 282 #define read_el2_ctx_vhe(ctx, reg) ULL(0) 283 #define write_el2_ctx_vhe(ctx, reg, val) 284 #define write_el2_ctx_vhe_sysreg128(ctx, reg, val) 285 #endif /* ENABLE_FEAT_VHE */ 286 287 #if ENABLE_FEAT_RAS 288 #define read_el2_ctx_ras(ctx, reg) (((ctx)->ras).reg) 289 #define write_el2_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 290 = (uint64_t) (val)) 291 #else 292 #define read_el2_ctx_ras(ctx, reg) ULL(0) 293 #define write_el2_ctx_ras(ctx, reg, val) 294 #endif /* ENABLE_FEAT_RAS */ 295 296 #if CTX_INCLUDE_NEVE_REGS 297 #define read_el2_ctx_neve(ctx, reg) (((ctx)->neve).reg) 298 #define write_el2_ctx_neve(ctx, reg, val) ((((ctx)->neve).reg) \ 299 = (uint64_t) (val)) 300 #else 301 #define read_el2_ctx_neve(ctx, reg) ULL(0) 302 #define write_el2_ctx_neve(ctx, reg, val) 303 #endif /* CTX_INCLUDE_NEVE_REGS */ 304 305 #if ENABLE_TRF_FOR_NS 306 #define read_el2_ctx_trf(ctx, reg) (((ctx)->trf).reg) 307 #define write_el2_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 308 = (uint64_t) (val)) 309 #else 310 #define read_el2_ctx_trf(ctx, reg) ULL(0) 311 #define write_el2_ctx_trf(ctx, reg, val) 312 #endif /* ENABLE_TRF_FOR_NS */ 313 314 #if ENABLE_FEAT_CSV2_2 315 #define read_el2_ctx_csv2_2(ctx, reg) (((ctx)->csv2).reg) 316 #define write_el2_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2).reg) \ 317 = (uint64_t) (val)) 318 #else 319 #define read_el2_ctx_csv2_2(ctx, reg) ULL(0) 320 #define write_el2_ctx_csv2_2(ctx, reg, val) 321 #endif /* ENABLE_FEAT_CSV2_2 */ 322 323 #if ENABLE_FEAT_HCX 324 #define read_el2_ctx_hcx(ctx, reg) (((ctx)->hcx).reg) 325 #define write_el2_ctx_hcx(ctx, reg, val) ((((ctx)->hcx).reg) \ 326 = (uint64_t) (val)) 327 #else 328 #define read_el2_ctx_hcx(ctx, reg) ULL(0) 329 #define write_el2_ctx_hcx(ctx, reg, val) 330 #endif /* ENABLE_FEAT_HCX */ 331 332 #if ENABLE_FEAT_TCR2 333 #define read_el2_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 334 #define write_el2_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 335 = (uint64_t) (val)) 336 #else 337 #define read_el2_ctx_tcr2(ctx, reg) ULL(0) 338 #define write_el2_ctx_tcr2(ctx, reg, val) 339 #endif /* ENABLE_FEAT_TCR2 */ 340 341 #if (ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) 342 #define read_el2_ctx_sxpoe(ctx, reg) (((ctx)->sxpoe).reg) 343 #define write_el2_ctx_sxpoe(ctx, reg, val) ((((ctx)->sxpoe).reg) \ 344 = (uint64_t) (val)) 345 #else 346 #define read_el2_ctx_sxpoe(ctx, reg) ULL(0) 347 #define write_el2_ctx_sxpoe(ctx, reg, val) 348 #endif /*(ENABLE_FEAT_S1POE || ENABLE_FEAT_S2POE) */ 349 350 #if (ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) 351 #define read_el2_ctx_sxpie(ctx, reg) (((ctx)->sxpie).reg) 352 #define write_el2_ctx_sxpie(ctx, reg, val) ((((ctx)->sxpie).reg) \ 353 = (uint64_t) (val)) 354 #else 355 #define read_el2_ctx_sxpie(ctx, reg) ULL(0) 356 #define write_el2_ctx_sxpie(ctx, reg, val) 357 #endif /*(ENABLE_FEAT_S1PIE || ENABLE_FEAT_S2PIE) */ 358 359 #if ENABLE_FEAT_S2PIE 360 #define read_el2_ctx_s2pie(ctx, reg) (((ctx)->s2pie).reg) 361 #define write_el2_ctx_s2pie(ctx, reg, val) ((((ctx)->s2pie).reg) \ 362 = (uint64_t) (val)) 363 #else 364 #define read_el2_ctx_s2pie(ctx, reg) ULL(0) 365 #define write_el2_ctx_s2pie(ctx, reg, val) 366 #endif /* ENABLE_FEAT_S2PIE */ 367 368 #if ENABLE_FEAT_GCS 369 #define read_el2_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 370 #define write_el2_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 371 = (uint64_t) (val)) 372 #else 373 #define read_el2_ctx_gcs(ctx, reg) ULL(0) 374 #define write_el2_ctx_gcs(ctx, reg, val) 375 #endif /* ENABLE_FEAT_GCS */ 376 377 #if CTX_INCLUDE_MPAM_REGS 378 #define read_el2_ctx_mpam(ctx, reg) (((ctx)->mpam).reg) 379 #define write_el2_ctx_mpam(ctx, reg, val) ((((ctx)->mpam).reg) \ 380 = (uint64_t) (val)) 381 #else 382 #define read_el2_ctx_mpam(ctx, reg) ULL(0) 383 #define write_el2_ctx_mpam(ctx, reg, val) 384 #endif /* CTX_INCLUDE_MPAM_REGS */ 385 386 #if ENABLE_FEAT_SCTLR2 387 #define read_el2_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg) 388 #define write_el2_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \ 389 = (uint64_t) (val)) 390 #else 391 #define read_el2_ctx_sctlr2(ctx, reg) ULL(0) 392 #define write_el2_ctx_sctlr2(ctx, reg, val) 393 #endif /* ENABLE_FEAT_SCTLR2 */ 394 395 #if ENABLE_BRBE_FOR_NS 396 #define read_el2_ctx_brbe(ctx, reg) (((ctx)->brbe).reg) 397 #define write_el2_ctx_brbe(ctx, reg, val) ((((ctx)->brbe).reg) \ 398 = (uint64_t) (val)) 399 #else 400 #define read_el2_ctx_brbe(ctx, reg) ULL(0) 401 #define write_el2_ctx_brbe(ctx, reg, val) 402 #endif /* ENABLE_BRBE_FOR_NS */ 403 404 /******************************************************************************/ 405 406 #endif /* __ASSEMBLER__ */ 407 408 #endif /* CONTEXT_EL2_H */ 409